SRAM Virtual Ground Circuit for Leakage Reduction and Data Retention
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Solution Overview
Problem
Existing solutions for reducing standby leakage current in SRAM memory circuits either increase the physical size of memory cells, require complex fabrication processes, or lack effective control over virtual ground voltage, compromising data retention reliability.
Innovation Solution
A system that maintains a virtual ground node in SRAM arrays by generating a threshold reference voltage based on the memory cell transistor's threshold voltage, using a multiplier circuit to produce a virtual ground reference voltage, and employing a leakage reduction circuit to regulate the virtual ground node, ensuring data retention while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistor stacks or self-reverse bias techniques are used to reduce leakage current, then leakage current is reduced significantly, but the memory cell area increases substantially
Solution Approach 1:
The patent changes the voltage parameter at the virtual ground node by dynamically adjusting it based on the threshold voltage of the memory cell transistor. By maintaining the virtual ground voltage at approximately one threshold voltage above ground potential, the patent achieves significant leakage current reduction without requiring additional transistors or increasing cell area, thus resolving the contradiction between energy loss reduction and area increase
2Device complexity
If simple gated-ground or virtual ground techniques are used, then implementation is simple, but control over the virtual ground voltage is poor
Solution Approach 1:
The patent implements a feedback mechanism where the virtual ground voltage is dynamically controlled based on the threshold voltage of the memory cell transistor. The system monitors the threshold voltage and adjusts the virtual ground voltage accordingly to maintain it at approximately one threshold voltage above ground potential. This feedback approach provides precise voltage control while maintaining data retention reliability, resolving the contradiction between simple implementation and reliable operation
3Loss of energy
If dynamic threshold voltage technique or body biasing is used, then leakage control is improved, but the fabrication process becomes more complicated requiring triple well process
Solution Approach 1:
The patent introduces a virtual ground node as an intermediary element that mediates between the power supply and the memory cell transistors. By controlling the voltage at this intermediate node, the patent achieves effective leakage current control without requiring complex triple well fabrication processes. The virtual ground acts as a mediator that enables leakage reduction through standard fabrication processes, resolving the contradiction between leakage control and manufacturing ease
Data Source
AI summary
A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.