SRAM Virtual Power Line Wake-Up Control
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Solution Overview
Problem
In static random access memory (SRAM) designs, simple daisy chain wake-up schemes fail to optimize the balance between peak current and time required for powering up bitcells and control circuits, leading to inefficiencies in power management.
Innovation Solution
The implementation of virtual power lines managed by Field Effect Transistor (FET) switches with delay circuits and wakeup detectors, which control the power connections to bitcells and control circuits, allowing for optimized power-up sequences that minimize peak current while ensuring timely activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple daisy chain wake-up schemes are used, then the device complexity is reduced, but the balance between peak current and wake-up time is not optimized
Solution Approach 1:
The patent segments the power management system into multiple independent virtual power lines, each controlled by separate FET switches and delay circuits. This segmentation allows granular control over power distribution to different bitcell groups, enabling optimization of peak current by activating power lines in a controlled sequence rather than simultaneously, thus resolving the contradiction between simplified structure and peak current optimization.
Solution Approach 2:
The patent implements preliminary action through delay circuits that pre-control the activation timing of FET switches. Before full power is applied to all bitcells, the system uses delay circuits to progressively enable virtual power lines, allowing the system to prepare and distribute power in a controlled manner that minimizes peak current while maintaining acceptable wake-up time.
2Device complexity
If simple daisy chain wake-up schemes are used, then the power management structure is simplified, but the wake-up time optimization is insufficient
Solution Approach 1:
The patent introduces dynamics into the power management system by making the activation sequence adjustable through delay circuits. Rather than a fixed daisy chain sequence, the system dynamically controls the timing of FET switch activation for each virtual power line, allowing optimization of wake-up time by adjusting delay parameters while maintaining structural simplicity.
Solution Approach 2:
The patent applies parameter changes by modifying the timing parameters of power activation through delay circuits. By changing the delay time parameters in the control logic, the system can optimize wake-up time without altering the fundamental simplified power management structure, thus resolving the contradiction between structural simplicity and wake-up time optimization.
3Use of energy by moving object
If virtual power lines with FET switches and delay circuits are implemented, then peak current is reduced, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing virtual power lines that serve multiple functions: they act as power distribution lines, timing control lines, and peak current management lines simultaneously. Each virtual power line with its FET switches and delay circuits performs multiple roles in the power management system, reducing the need for separate dedicated components and thus mitigating the increase in device complexity while maintaining peak current reduction benefits.
4Loss of time
If virtual power lines with FET switches and delay circuits are implemented, then wake-up time is optimized, but the device complexity increases
Solution Approach 1:
The patent uses delay circuits as intermediary elements between the control logic and the FET switches. These intermediary delay circuits provide precise timing control for power activation, optimizing wake-up time by mediating the signal transmission and enabling controlled sequential activation of virtual power lines, while keeping the overall architecture manageable through the use of standardized intermediary components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces peak current consumption and optimizes the time required for SRAM devices to wake up from sleep mode, improving power management efficiency and aligning with System-On-Chip (SOC) power capacity considerations.
Implementation Method 1
The implementation of virtual power lines managed by Field Effect Transistor (FET) switches with delay circuits and wakeup detectors, which control the power connections to bitcells and control circuits
Data Source
AI summary
A device includes a virtual power line directly connected to each bitcell in a group of bitcells and a group of transistor switches connected between the virtual power line and a power supply. The device also includes a delay circuit, a first wakeup detector, and a plurality of main input-output (MIO) controllers. The delay circuit is coupled to the gate terminal of each transistor switch of the group of transistor switches. The first wakeup detector is configured to generate a first trigger signal in response to receiving a signal from the delay circuit. The plurality of main input-output (MIO) controllers is configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches. A gate terminal of each wakeup switch in the first group of wakeup switches is configured to receive the first trigger signal.