SRAM Vmin Measurement Using Multiplexed Voltage Control
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Solution Overview
Problem
Current semiconductor integrated circuit testing methods, particularly for SRAM cells, face challenges in accurately determining minimum and maximum operating voltages due to parasitic elements causing inaccurate results and overshoot issues, which affect the reliability and cost-effectiveness of memory cell operation.
Innovation Solution
A parametric test circuit with a latch circuit and multiplex circuit that applies controlled voltage steps to isolate overshoot effects, ensuring accurate measurement of memory cell operating voltages by resetting the data state before measurement and using analog multiplexing to minimize parasitic inductance and overshoot impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage steps are applied to measure memory cell operating parameters, then measurement capability is enabled, but parasitic elements cause overshoot and measurement inaccuracy
Solution Approach 1:
The patent applies preliminary action by resetting the data state of the memory cell to a known state before each voltage step measurement. This ensures that the cell is in a predictable initial condition, eliminating the effects of previous states on current measurements and preventing overshoot-related inaccuracies.
Solution Approach 2:
The patent implements periodic action through a systematic measurement sequence where voltage steps are applied in a controlled, repeating pattern. Each measurement cycle includes setting a specific voltage level, allowing stabilization, performing the measurement, and resetting the state, which minimizes parasitic effects by maintaining consistent timing and state transitions.
2Measurement precision
If complex production testers are used to determine memory pattern sensitivity, then measurement capability is improved, but testing cost increases
Solution Approach 1:
The patent applies self-service by implementing measurement and reset functions within the memory cell structure itself. The circuit uses internal nodes and transistors to perform self-diagnosis and state resetting, eliminating the need for external complex test equipment while maintaining accurate measurement capabilities.
Solution Approach 2:
The patent achieves multi-functionality by designing a test circuit that can perform multiple measurement functions (Vmin, Vmax, trip voltage) using the same basic structure. This universal approach allows a single simplified circuit to replace multiple specialized test systems, reducing overall complexity and cost.
3Productivity
If sub-micron feature sizes and reduced operating voltages are used, then circuit integration is improved, but determination of operating parameters becomes more difficult
Solution Approach 1:
The patent applies local quality by creating dedicated test structures with specific local characteristics that differ from the main memory array. These test structures have optimized geometries and configurations that enhance the visibility and measurability of operating parameters at sub-micron dimensions, making detection easier without affecting overall integration density.
Data Source
AI summary
A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor (208) has a current path connected between the complementary terminal and a second access terminal (216) and has a second control terminal connected to the first control terminal. A multiplex circuit (804) is arranged to apply a first voltage (VDD1) to the first power supply terminal in response to a first state of a select signal (SEL) and to apply a second voltage (VDD2) to the first power supply terminal in response to a second state of a select signal.