SRAM Voltage Adjustment Circuits for Leakage Reduction
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Solution Overview
Problem
SRAM devices face a trade-off between low power consumption and high density, as reducing leakage currents on bit lines by limiting the number of memory cells per bit line degrades memory cell density, requiring additional circuits and increasing area requirements.
Innovation Solution
The memory device divides its cell array into areas with separate voltage adjustment circuits for each bit line, allowing reference nodes to be adjusted to ground or a reference voltage level based on access operations, eliminating leakage currents and enabling higher memory cell density without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the number of memory cells coupled to each bit line is limited to reduce leakage currents, then power consumption is reduced, but memory cell density degrades
Solution Approach 1:
The memory cell array is divided into multiple banks, and each bank is further divided into multiple regions. Separate voltage adjustment circuits are provided for each region, allowing independent voltage control. This segmentation enables different regions to be accessed independently, reducing leakage current in non-accessed regions while maintaining high memory cell density through efficient bit line utilization.
Solution Approach 2:
Different voltage adjustment circuits are applied to different regions of the memory cell array based on local access requirements. When a specific region is accessed, only the voltage adjustment circuits for that region are activated, while other regions maintain their reference voltage levels. This local quality approach minimizes leakage current in non-accessed regions without affecting the density of the entire memory array.
2Quantity of substance
If additional local control circuits and local input/output circuits are added to increase memory cell density, then memory cell density is improved, but area requirements increase
Solution Approach 1:
The voltage adjustment circuits are merged with the existing memory cell structure and share control logic with the memory cell array. The divided banks and regions allow multiple memory cells to be accessed through shared bit lines without requiring separate control circuits for each cell group. This merging approach increases memory cell density while minimizing additional area requirements.
3Quantity of substance
If more bit lines are added to increase memory cell density, then memory cell density is improved, but power consumption increases due to increased leakage currents
Solution Approach 1:
The voltage adjustment circuits dynamically adjust the voltage levels at reference nodes based on access operations. When a region is not being accessed, the voltage adjustment circuits maintain reference voltage levels that minimize leakage currents. When a region is accessed, the voltage adjustment circuits switch to appropriate voltage levels for read/write operations. This dynamic voltage adjustment allows more memory cells to be coupled to each bit line without proportionally increasing power consumption.
Data Source
AI summary
A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.