SRAM Voltage Assist via Capacitive Charge Coupling
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Solution Overview
Problem
Existing SRAM devices face challenges in reliably reading from and writing to cells due to increased variability from fabrication tolerances and operating conditions, leading to potential corruption of memory states, especially with decreasing voltages and physical dimensions, which existing voltage assist mechanisms address inadequately by consuming significant power and being overly large.
Innovation Solution
The implementation of dynamic voltage boost mechanisms that selectively apply voltage based on the addressed SRAM cell, using capacitively coupled charge on wordlines and bitlines, eliminating the need for an auxiliary supply and allowing for variable voltage levels, thereby reducing power consumption and physical size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing voltage assist mechanisms are used to improve read and write reliability, then the ability to read from and write to SRAM cells is improved, but the assist circuitry becomes relatively large and consumes significant power
Solution Approach 1:
The patent implements dynamic voltage assist by selectively enabling boost circuitry only for specific wordlines or bitlines that require assistance, rather than continuously powering all assist circuits. The control logic dynamically determines which lines need voltage boosting based on operational needs, thereby maintaining reliability while reducing overall power consumption.
Solution Approach 2:
The patent applies voltage assist locally to specific wordlines or bitlines that require it, rather than globally to the entire SRAM array. By using selective boost circuitry controlled by decode logic, only the necessary portions of the circuit receive enhanced voltage, reducing unnecessary power consumption in areas that don't require assistance.
2Reliability
If existing voltage assist mechanisms are designed for worst case scenarios to account for fabrication variations, then read and write reliability is improved, but the assist circuitry becomes relatively large
Solution Approach 1:
The patent implements selective voltage assist that applies boosting only to specific wordlines or bitlines that require it, rather than providing universal assistance to the entire SRAM array. This localized approach reduces the overall area of assist circuitry needed while maintaining reliability for the specific lines that require enhancement.
Solution Approach 2:
The patent uses dynamic control logic to selectively enable boost circuitry only when and where needed, rather than maintaining a static, always-on assist infrastructure. This dynamic activation reduces the effective area required for assist circuitry by allowing shared resources and selective activation of boosting components.
3Reliability
If voltage assist is continuously applied to all wordlines and bitlines, then the ability to prevent inadvertent flipping is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic or selective voltage assist rather than continuous application. The boost circuitry is activated only during specific operations on specific lines that require assistance, and remains inactive otherwise. This periodic activation maintains data integrity when needed while avoiding continuous power waste.
Solution Approach 2:
The patent applies voltage assist locally to specific wordlines or bitlines that require protection from inadvertent flipping, rather than continuously boosting all lines. The selective boost circuitry targets only the necessary portions of the circuit, maintaining data integrity for vulnerable lines while avoiding unnecessary power consumption in lines that don't require assistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of read and write operations while minimizing power usage and physical size by providing voltage assist only as needed, improving performance without sacrificing reliability.
Implementation Method 1
using capacitively coupled charge on wordlines and bitlines
Data Source
AI summary
The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines. The SRAM array further includes voltage boost circuitry operatively coupled with the cells, the voltage boost circuitry being configured to provide an amount of voltage boost that is based on an address of a cell to be accessed and/or to provide this voltage boost on an SRAM line via capacitive charge coupling.