SRAM Array Voltage Boosting for Stability and Power
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Solution Overview
Problem
Integrated circuits face challenges in maintaining SRAM cell stability at lower power supply voltages, leading to increased susceptibility to soft errors and process variations, which reduces production yields and increases power consumption when SRAM arrays are operated at higher voltages to compensate.
Innovation Solution
The implementation of a system where charge pumps provide a selectively boosted supply voltage to SRAM memory arrays, with voltage detectors monitoring and adjusting the voltage to ensure stability, allowing only those arrays needing a boosted voltage to receive it, thereby improving production yields while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM arrays are operated at higher voltage to improve stability, then SRAM cell stability is improved, but power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different SRAM arrays based on their individual stability requirements. Each array can be independently configured to receive either normal supply voltage or boosted voltage, allowing only those arrays that need enhanced stability to consume additional power. This is achieved through separate charge pump circuits and voltage selection logic for each array.
Solution Approach 2:
The patent implements dynamic voltage selection where the voltage level supplied to each SRAM array can be adjusted based on measured stability characteristics. During fabrication or initialization, arrays are tested and configured to receive appropriate voltage levels, allowing the system to adapt to process variations and optimize the trade-off between stability and power consumption.
2Use of energy by moving object
If lower power supply voltages are used to reduce power consumption, then power consumption is reduced, but SRAM cell stability deteriorates
Solution Approach 1:
The patent enables different SRAM arrays to operate at different voltage levels according to their specific stability requirements. Arrays that can operate reliably at lower voltages do so, reducing overall power consumption, while arrays that require higher voltages for stability receive boosted supply through dedicated charge pumps.
Solution Approach 2:
The system dynamically configures voltage levels for each SRAM array based on measured performance characteristics. This allows the circuit to operate at the lowest possible voltage for each array while maintaining stability, optimizing the power-consumption versus stability trade-off.
3Use of energy by moving object
If SRAM arrays are operated at lower voltages to reduce power consumption, then power consumption is reduced, but production yields decrease
Solution Approach 1:
The patent compensates for process variations by providing individualized voltage boosting to SRAM arrays that fail to meet stability requirements at nominal voltage. This per-array compensation approach allows the circuit to operate at lower overall power consumption while maintaining high production yields by salvaging arrays that would otherwise be rejected.
Solution Approach 2:
The patent changes the operating voltage parameter for individual SRAM arrays based on their measured stability characteristics. Arrays exhibiting marginal stability at nominal voltage are supplied with boosted voltage, transforming them from defective units into functional devices, thereby improving production yields without increasing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability of SRAM cells and reduces power consumption by selectively applying a boosted voltage only to arrays that require it, thereby improving production yields and maintaining performance at lower power supply voltages.
Implementation Method 1
A charge pump and voltage detector are associated with each memory array. The charge pumps are each independently controlled to selectively provide a boosted supply voltage to supply voltage terminals of the memory cells.
Implementation Method 2
A voltage detector is coupled to an output of each of the charge pumps to detect the boosted supply voltage. In response to detecting that the boosted supply voltage is below a predetermined voltage, the voltage detector causes the charge pump to increase the supply voltage of a memory array associated with the charge pump.
Data Source
AI summary
An integrated circuit comprises a global power supply conductor, a plurality of circuit blocks, a plurality of voltage converters, and control logic. The global power supply conductor is configured to distribute a supply voltage. The circuit blocks are selectively coupled to the global power supply conductor. The plurality of voltage converters are coupled to the global power supply conductor. An output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more of the plurality of circuit blocks. The control logic is configured to control the selective coupling of at least one of the supply voltage and the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks. Also, the control logic controls a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters.