SRAM Cell Voltage Boosting for Read Speed and Power
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Solution Overview
Problem
Conventional SRAM cells face performance degradation and high array power dissipation issues, especially with reduced supply voltages, due to decreased current-driving capability and large bit line capacitance, which are not effectively addressed by existing solutions such as the 5T cell or thin-cell designs.
Innovation Solution
The proposed SRAM design employs a power supply circuit that applies different voltage differences across multiple power supply rails during read or write phases, with a bit line pre-charge circuit generating a voltage within 10% of the intermediate level between the first and second voltages, and a word line activation circuit rendering the first transistor conductive with a higher voltage, thereby enhancing read and write speeds and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If reduced VDD supply voltage is used, then power consumption is reduced, but read operation speed degrades rapidly due to decreasing current-driving capability
Solution Approach 1:
The patent implements dynamic voltage boosting by introducing a boosted voltage signal (VBST) that is applied to the bit line during read operations. This dynamic voltage adjustment allows the system to operate at low VDD for power savings while providing temporary voltage enhancement during critical read operations to maintain speed performance.
Solution Approach 2:
The patent changes the voltage parameter by introducing a boosted voltage level that exceeds the normal VDD supply voltage. This parameter change enables the memory cell to overcome threshold voltage limitations and maintain adequate drive current even when operating from reduced supply voltages.
2Use of energy by moving object
If conventional 6T cell is used with reduced VDD, then power consumption decreases, but gate-over-drive capability becomes insufficient due to Vt variations
Solution Approach 1:
The patent dynamically adjusts the effective voltage across the memory cell by applying the boosted voltage to the bit line. This dynamic adjustment compensates for threshold voltage variations and ensures adequate gate-over-drive capability during read operations while maintaining low power consumption during standby.
Solution Approach 2:
The boosted voltage signal acts as an intermediary that mediates between the low VDD supply and the requirements for adequate drive capability. By introducing this intermediate voltage level, the system can operate from low voltage while still achieving the necessary drive strength during critical operations.
3Reliability
If full VDD voltage swing is applied to bit lines, then read operation margin is improved, but array power dissipation increases significantly
Solution Approach 1:
The patent changes the voltage swing parameter by applying the boosted voltage (VBST) instead of the full VDD swing to the bit line during read operations. This parameter change provides adequate read margin while reducing the energy consumed during bit line charging and discharging cycles.
Solution Approach 2:
The boosted voltage is applied periodically only during read operations rather than continuously. This periodic application provides the necessary read margin when needed while minimizing power consumption during non-read periods, achieving a balance between reliability and energy efficiency.
Data Source
Figure 1A~1C
Figure 2A~2B
Figure 3A~4B
AI summary
The invention concerns a static random access memory (SRAM) comprising: a plurality of memory cells each having a pair of cross-coupled inverters (102, 104), a first of the inverters (102) being supplied by first and second power supply rails (VDD, VSS) and a second of the inverters (104) being supplied by third and fourth supply rails (114, 116), an input of the second inverter (102) being coupled to a first bit line (BL, WBL) via a first transistor (118); and a power supply circuit (120) adapted to apply a first voltage difference (VDD) across the first and second power supply rails (VDD, VSS) and a second voltage difference (VDH, VSL) across the third and fourth power supply rails (114, 116), the second voltage difference being greater than the first voltage difference.