SRAM Voltage Control Circuit Reducing Parasitic Resistance
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Solution Overview
Problem
Conventional SRAM devices experience voltage degradation due to parasitic resistance in metal routing lines, leading to performance issues such as degraded logic levels and potential read/write failures, especially in longer SRAM cell columns where the voltage drop can be substantial.
Innovation Solution
A voltage control circuit is implemented within the SRAM device to provide a low-resistance path for bit line and bit line bar signal lines, reducing parasitic resistance by allowing SRAM cells at the far end to receive Vss through a shorter path via additional pass gates during write cycles, thereby alleviating voltage loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the SRAM array is extended to increase storage capacity, then the array efficiency is improved, but the parasitic resistance of metal routing increases causing voltage degradation
Solution Approach 1:
The bit line is segmented into multiple sections by inserting intermediate bit line taps at regular intervals along the bit line. Each segment connects to a separate sense amplifier, dividing the long bit line into shorter segments. This segmentation reduces the parasitic resistance impact on any single segment while maintaining the overall storage capacity of the extended array.
Solution Approach 2:
Intermediate bit line taps serve as intermediary connection points between the extended SRAM array and sense amplifiers. These taps act as mediators that provide multiple access points along the bit line, reducing the effective resistance path for any given memory cell while enabling the array to be extended without proportionally increasing voltage degradation.
2Ease of manufacture
If conventional memory devices are used, then manufacturing simplicity is maintained, but voltage degradation causes degraded logic levels and potential read/write failures
Solution Approach 1:
The patent implements preliminary voltage compensation by providing multiple sense amplifiers connected to intermediate bit line taps before voltage degradation can critically affect memory operations. This preliminary action ensures that voltage levels are restored and maintained within acceptable ranges before read/write operations occur, preventing logic level degradation and ensuring reliable operation without complicating the manufacturing process.
Data Source
AI summary
An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.