SRAM Supply Voltage Control for Stability
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Solution Overview
Problem
Static random access memory (SRAM) cells face challenges in maintaining stability during read and write operations due to transistor threshold voltage mismatch, leading to susceptibility to noise and reduced stability, which existing methods attempt to address through transistor sizing or additional voltage generators, but these solutions either increase cell area or reduce read/write speed.
Innovation Solution
Implementing a system that includes error detection circuitry to identify unstable memory cells and selectively increase the supply voltage for those cells, thereby improving stability without affecting all memory cells, thus reducing power consumption and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor sizing or additional voltage generators are used to improve stability, then stability is improved, but cell area increases or read/write speed decreases
Solution Approach 1:
The patent applies dynamics by making the supply voltage adjustable rather than fixed. The system dynamically switches between a first supply voltage for normal operations and a second supply voltage (higher than the first) for error correction operations. This allows the memory cell to adapt its operating conditions based on the specific task requirements, improving stability when needed without permanently sacrificing read/write speed.
Solution Approach 2:
The patent changes the electrical parameter of supply voltage to resolve the contradiction. By varying the supply voltage between two distinct levels (first supply voltage for normal operation, second supply voltage for error correction), the system can optimize stability during error correction without permanently degrading performance during normal read/write operations.
2Reliability
If additional voltage generators are added to improve stability, then stability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single memory cell structure that performs multiple functions: normal read/write operations at the first supply voltage and error correction operations at the second supply voltage. This eliminates the need for separate voltage generators for different operations, as the same cell structure handles both tasks by simply changing the supply voltage level.
Solution Approach 2:
The patent avoids increasing device complexity by using parameter changes (supply voltage switching) rather than adding physical components. The error correction functionality is achieved by changing the operational parameter (voltage level) of the existing memory cell, not by adding separate voltage generation circuits for each operation type.
3Reliability
If supply voltage is increased for all memory cells to improve stability, then stability is improved, but power consumption and heat dissipation increase
Solution Approach 1:
The patent applies local quality by providing different supply voltages to different memory cells based on their operational state. Memory cells undergoing error correction operations receive the higher second supply voltage, while memory cells performing normal operations continue to receive the lower first supply voltage. This selective voltage application improves stability where needed without unnecessarily increasing power consumption across the entire memory array.
Solution Approach 2:
The patent applies partial action by increasing the supply voltage only for the subset of memory cells that require error correction, rather than uniformly increasing the voltage for all cells. This partial voltage increase provides the necessary stability improvement for affected cells while minimizing the overall power consumption and heat dissipation impact.
Data Source
AI summary
Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.