Low-Power SRAM Voltage Domain Adaptation for AI Memory
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Solution Overview
Problem
There is a need to reduce power dissipation in SRAMs, particularly in at-memory compute architectures where SRAMs are located on-chip adjacent to processing elements, and operate at low voltages to support high throughput and low power consumption for AI hardware acceleration.
Innovation Solution
The solution involves an SRAM system that operates at two different low voltage domains, with a 6T bit cell voltage set to the standard cell voltage during read operations and to the processing element operating voltage during write operations, using adaptive voltage supplies and charge sharing techniques to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the SRAM operates at low voltage (0.35V) to reduce power consumption, then power dissipation is reduced, but the reliability of read operations deteriorates due to insufficient bit cell voltage
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bit cell voltage based on operation mode. During read operations, the bit cell voltage is boosted to 0.75V (higher than PE voltage) to ensure reliable reading, while during write operations, it is reduced to match the PE voltage (0.35V) to minimize power consumption. This selective parameter adjustment resolves the contradiction between power savings and read reliability.
Solution Approach 2:
The patent implements dynamics by making the voltage supply adaptive rather than fixed. A cell vdd selector circuit dynamically switches between different voltage levels (0.35V for writes, 0.75V for reads) based on the operational state. This dynamic voltage adjustment allows the system to optimize both power consumption and reliability according to the specific operation requirements.
2Loss of energy
If the bit line precharge voltage is reduced to minimize power consumption, then power dissipation is reduced, but the throughput of read operations deteriorates
Solution Approach 1:
The patent applies parameter changes by setting the bit line precharge voltage to a specific value (0.1V) that is lower than half of the PE voltage. This reduced precharge voltage significantly lowers the power consumption of the bit line precharge circuit while the system maintains acceptable read throughput through optimized read operation timing and voltage boosting during actual read cycles.
3Productivity
If the SRAM is integrated on-chip adjacent to processing elements in at-memory architecture, then bandwidth and throughput are improved, but power consumption increases due to proximity of high-power bit line precharge circuits
Solution Approach 1:
The patent applies parameter changes by operating the SRAM at reduced voltages (0.35V for writes, 0.75V for reads with boosted word lines) compared to traditional high-voltage memory operations. This voltage reduction significantly lowers the power consumption of the SRAM cell array and its associated circuits, enabling high-bandwidth at-memory architecture to achieve high TOPS/W performance.
Solution Approach 2:
The patent implements local quality by applying different voltage levels to different parts of the system based on their functional requirements. The processing elements operate at 0.35V for low power, while the SRAM bit cell voltage is boosted to 0.75V during reads to ensure reliability. The bit line precharge circuit operates at a reduced 0.1V during read operations to minimize power consumption, creating localized optimization throughout the system.
Data Source
AI summary
A low-power static random access memory (SRAM) for at-memory architecture is described. The SRAM in at-memory architecture is located adjacent to a Processing Element (PE) so that the same voltage is required at the SE and the SRAM connected to the PE. However, SRAM read/write operation needs different voltage than the PE. Accordingly, selective voltage supplies are described including adaptive voltage supplies (AVS). A bitline precharge level of 0.1V is described for ultra-low power. Moreover, to reduce the number of supply voltages, the bit cell voltage is set at standard cell voltage, Vddc for read, and at a PE operating voltage Vddp for a write.