SRAM Voltage Multiplexing for Standby Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit memory power supplies face challenges in minimizing power consumption, particularly in standby mode, due to leakage currents, which are exacerbated by conventional high voltage settings, especially in battery-powered devices and large memory arrays.
Innovation Solution
A circuit that selectively applies different sets of voltages to memory cells based on operational mode, using multiplexing circuitry to switch between high and low voltage supply nodes, reducing leakage current by adjusting voltage levels when in standby mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional high voltage settings are applied to SRAM cells, then performance and speed are improved, but power consumption and leakage currents increase
Solution Approach 1:
The patent implements dynamic voltage scaling by switching between two sets of power supply voltages (first set with higher VDH and VDL for active mode, second set with lower VDH and VDL for standby mode). This dynamic adjustment of voltage levels allows the memory device to optimize performance during active operations while minimizing power consumption during standby periods, directly resolving the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the voltage parameters (VDH and VDL) based on operational mode. During active mode, higher voltage parameters are used to maintain fast operation speed. During standby mode, lower voltage parameters are applied to reduce leakage currents and power consumption. This parameter switching mechanism effectively balances performance and energy efficiency.
2Reliability
If conventional high voltage settings are applied to SRAM cells, then memory operation reliability is improved, but leakage currents increase
Solution Approach 1:
The patent dynamically switches voltage levels based on operational state. During standby mode, lower voltage settings reduce the electric field strength across transistors, thereby minimizing leakage currents while maintaining data retention. During active mode, higher voltages ensure reliable read/write operations. This dynamic approach maintains reliability while reducing harmful leakage effects.
Solution Approach 2:
The patent modifies voltage parameters (VDH and VDL) according to operational mode. In standby mode, reduced voltage parameters minimize transistor leakage without compromising data integrity. In active mode, full voltage parameters ensure reliable memory operations. This parameter adaptation resolves the conflict between reliability and leakage current reduction.
3Use of energy by moving object
If voltage levels are reduced during standby mode, then power consumption is minimized, but memory performance may be degraded
Solution Approach 1:
The patent implements dynamic voltage scaling where lower voltages are applied during standby mode to minimize power consumption, and higher voltages are quickly restored during active mode to ensure fast memory access. The rapid switching capability ensures that performance degradation is avoided during actual operations while achieving power savings during idle periods.
Solution Approach 2:
The patent employs periodic switching between voltage sets based on operational demands. During standby periods, lower voltages are applied to reduce power consumption. When memory access is required, the system quickly transitions to higher voltage settings to restore full performance. This periodic voltage adjustment strategy optimizes the balance between power savings and performance maintenance.
Data Source
AI summary
A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.