Multi-port SRAM Module Voltage Control for Read Disturb
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Solution Overview
Problem
Conventional dual-port SRAM modules face issues such as read disturb, degraded write margin, and high leakage current due to simultaneous read and write operations, leading to instability in data retention.
Innovation Solution
A multi-port SRAM module design that includes a memory cell array with a first and second word line, and a switch or detection circuit to adjust voltage levels, allowing for asynchronous operation and reducing read disturb by controlling the voltage levels of the word lines and bit lines, thereby enhancing stability during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual port memory cells are connected to the same word lines for simultaneous read and write operations, then access speed is enhanced, but read static noise margin is degraded due to double read disturb
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage levels of word lines based on the operational state of memory cells. When a memory cell is in data-retaining state, the word line voltage is reduced to minimize leakage current and prevent read disturb, thereby maintaining read static noise margin while still allowing fast access when needed
2Speed
If read and write operations are performed simultaneously on dual port memory cells, then access speed is improved, but write margin is degraded due to current competition
Solution Approach 1:
The patent implements dynamics by making the word line voltage levels adaptive and dynamic rather than fixed. The voltage levels change based on the operational mode (read, write, or data-retaining state), allowing the system to optimize for either speed or reliability depending on the current operation, thus resolving the contradiction between simultaneous read/write speed and write margin
3Speed
If two word lines of the same row are asserted simultaneously, then access speed is enhanced, but data retention stability is degraded due to increased leakage current
Solution Approach 1:
The patent uses parameter changes by adjusting word line voltage levels according to the operational state. When memory cells are in data-retaining state, the voltage is reduced to minimize leakage current and maintain stability. This allows the system to prevent data loss while still enabling fast access operations when data is being actively read or written
Data Source
AI summary
A multi-port SRAM module includes a cell array comprising a plurality of cells, each having a first port and a second port; a first word line which is coupled to a plurality of cells of a target row to open and close the first port; a second word line which is coupled to the cells of the target row to open and close the second port; and a switch, which is coupled to the first word line and the second word line and couples the second word line to a reference voltage level according to a voltage level of the first word line.