SRAM Voltage Scaling for Low-Power Write Stability and Yield
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Solution Overview
Problem
The increasing gap between processor frequencies and DRAM access times leads to higher power usage in computing devices, particularly due to the prevalent use of SRAM, which affects battery life and memory access success rates.
Innovation Solution
Implementing a system with voltage scaling for memory supply voltages and wordline voltages in SRAM cells to reduce power consumption while maintaining memory stability and performance, using level shifters and voltage scaling circuits to adjust voltages based on usage models and process corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage is reduced to lower power consumption, then power usage decreases, but memory access success rate deteriorates
Solution Approach 1:
The patent implements dynamic voltage scaling that adjusts memory supply voltage based on operation type (read/write) and process corner conditions. During read operations, voltage is maintained at higher levels to ensure access success, while during write operations, voltage is scaled down to reduce power consumption. This dynamic adjustment resolves the contradiction by making voltage adaptive rather than static.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on operational requirements and process variations. By monitoring process corners and operation types, the system adjusts voltage levels to optimize both power consumption and access success rate, transforming a fixed parameter into a variable one that adapts to conditions.
2Productivity
If SRAM usage is increased to meet performance targets, then processing performance improves, but power consumption increases
Solution Approach 1:
The patent applies voltage scaling to SRAM operations to reduce power consumption while maintaining performance. By adjusting voltage based on operation type and process corner, the system achieves lower power consumption for the same processing performance, resolving the contradiction between productivity and energy usage.
Solution Approach 2:
The patent implements periodic voltage adjustment based on operation cycles, switching between different voltage levels for read/write operations. This periodic voltage modulation allows performance to be maintained during critical operations while reducing power during less demanding operations.
3Use of energy by stationary object
If voltage scaling is implemented to reduce power, then power consumption decreases, but static noise margin deteriorates
Solution Approach 1:
The patent carefully controls voltage scaling parameters to maintain static noise margin above threshold levels. By adjusting voltage within specific ranges and considering process corners, the system achieves power reduction while preserving sufficient noise margin for reliable operation.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor process corners and operational conditions to determine appropriate voltage scaling levels. This feedback ensures that voltage is reduced only to levels that maintain adequate static noise margin, preventing deterioration while achieving power savings.
Data Source
AI summary
A system for low power, high yield memory is described. The system includes a memory cell configured to receive a memory supply voltage. The system further includes a memory supply voltage control circuit configured to modify the memory supply voltage from a first memory supply voltage level to a second memory supply voltage level for a write to the memory cell.