SRAM Testing via Voltage Stress to Reduce Overkill
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Solution Overview
Problem
The high cost of low-temperature screening tests for SRAM semiconductor devices due to the need for specialized cooling facilities and increased testing time, which can lead to overkill and incorrect identification of non-defective chips as defective, especially in miniaturized semiconductor elements with significant local variation.
Innovation Solution
Implementing a pseudo-low-temperature screening test at normal temperatures by adjusting the power supply voltage to simulate low-temperature conditions, using an intermediate potential to selectively stress the SRAM memory cell and prevent overkill, thereby reducing the risk of defective chip identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low-temperature screening test is performed on SRAM semiconductor devices, then defects at low temperature can be detected, but testing costs and time increase significantly due to specialized cooling facilities
Solution Approach 1:
The patent changes the temperature parameter from low temperature to normal temperature, and compensates by adjusting the power supply voltage parameter. By applying a lowered power supply voltage (e.g., 0.9V instead of 1.0V) at normal temperature, the test simulates low-temperature conditions where defects become apparent, thereby maintaining defect detection accuracy while eliminating the need for cooling facilities and reducing testing time
2Productivity
If a normal temperature test is performed instead of low temperature test, then testing costs and time are reduced, but the risk of overkill increases where non-defective chips are incorrectly identified as defective
Solution Approach 1:
The patent carefully adjusts the power supply voltage parameter to a specific lowered value that creates an intermediate operating condition. This voltage level is high enough to allow non-defective chips to operate normally (avoiding overkill) but low enough to expose defects that would only manifest at low temperatures. The precise voltage control enables discrimination between defective and non-defective chips at normal temperature
Solution Approach 2:
The patent creates a virtual copy of low-temperature operating conditions by using a lowered power supply voltage at normal temperature. This voltage-stress condition replicates the electrical characteristics and defect manifestation patterns of low-temperature operation without requiring actual thermal conditions, thereby maintaining detection accuracy while improving testing efficiency
3Productivity
If miniaturized semiconductor elements are used, then device integration is improved, but local variation increases making low temperature defects more common
Solution Approach 1:
The patent applies a lowered power supply voltage parameter to create stress conditions that amplify the effects of local variation in miniaturized elements. This voltage stress causes circuits with poor static noise margin (SNM) due to manufacturing variations to fail, while well-designed circuits continue to operate. This enables detection of miniaturization-related defects at normal temperature without requiring low-temperature testing
Data Source
AI summary
When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.