Dynamic Source Voltage Adjustment for SRAM Writing Accuracy
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Solution Overview
Problem
Conventional static random access memory (SRAM) units with a single bit line experience rewriting errors due to instability when attempting to write data with a high voltage level, as the NMOS transistor fails to turn on completely and the PMOS transistor fails to turn off completely, leading to incorrect voltage levels at points B and C.
Innovation Solution
A source power supply circuit that provides different source voltages to the memory unit, specifically adjusting the voltage levels based on the write enable signal and word line signals to ensure the NMOS transistor is fully turned on during writing and the correct voltage is maintained during reading, preventing rewriting errors by offering Vdd-VTN during writing and Vdd during reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory unit uses a single bit line with conventional voltage levels, then the structure is simple, but rewriting errors occur when attempting to write data with high voltage level
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the source voltage level based on the operation mode. During write operations, the source voltage is lowered to Vdd-VTN to ensure the NMOS transistor can fully turn on and drive the bit line to the required voltage level, preventing rewriting errors. During read operations, the source voltage is restored to Vdd to maintain correct voltage levels for accurate reading. This dynamic parameter adjustment resolves the contradiction between simple structure and reliable operation.
Solution Approach 2:
The patent implements dynamics by making the source voltage adjustable rather than fixed. The source power supply circuit responds to control signals (such as write enable and word line signals) to dynamically switch between two voltage levels: Vdd during read operations and Vdd-VTN during write operations. This dynamic voltage adjustment enables the memory unit to adapt to different operational requirements, ensuring both writing accuracy and reading correctness without increasing structural complexity.
2Reliability
If the NMOS transistor is fully turned on during writing by adjusting beta ratio, then writing accuracy improves, but memory unit stability deteriorates
Solution Approach 1:
Instead of permanently adjusting transistor parameters (beta ratio) which compromises stability, the patent changes the operating parameter (source voltage) dynamically. By lowering the source voltage to Vdd-VTN during write operations, the patent ensures the NMOS transistor receives sufficient gate-to-source voltage to turn on completely, achieving accurate writing without altering the transistor's physical characteristics. This approach maintains memory unit stability while ensuring writing accuracy.
Solution Approach 2:
The patent uses dynamic voltage adjustment rather than static transistor parameter modification. The source power supply circuit dynamically switches the source voltage between Vdd and Vdd-VTN based on operation mode, allowing the NMOS transistor to operate optimally during writing (fully turned on) and maintaining stability during normal operation. This dynamic approach avoids the stability issues caused by permanent beta ratio adjustments.
3Reliability
If different voltage levels are provided for reading and writing, then rewriting errors are prevented, but power supply circuit complexity increases
Solution Approach 1:
The patent implements a dynamic power supply circuit that adjusts the source voltage based on operation mode. The circuit includes a power supply unit with output端 connected to the memory unit, and control logic that responds to write enable signals and word line signals to switch between Vdd and Vdd-VTN. This dynamic adjustment prevents rewriting errors while keeping the circuit relatively simple by using existing control signals to drive the voltage switching, rather than requiring completely separate power supply circuits for read and write operations.
Data Source
AI summary
A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error.