Built-In SRAM Wafer Test Circuit Without Dedicated ATE
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Solution Overview
Problem
Existing wafer acceptance test (WAT) equipment for static memory function tests requires dedicated machines, leading to high costs and complex procedures, as it cannot perform AC tests and can only measure DC characteristics, necessitating custom-designed chips and additional hardware for functional tests.
Innovation Solution
A reduced instruction built-in self-test circuit formed on the wafer, comprising a ring oscillator, frequency divider, counter, and data latch and comparator, which operates under DC voltage to perform internal clock signal generation and data comparison, allowing for self-testing of static memory without relying on dedicated test machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ATE equipment is used for static memory function test, then test capability is achieved, but equipment cost increases and test procedure becomes complicated
Solution Approach 1:
The patent implements a self-test mechanism where the static memory chip performs its own functional testing using an integrated test circuit that generates test patterns, applies them to the memory array, and evaluates results without requiring external ATE equipment. This eliminates the need for expensive dedicated test machines and simplifies the testing process.
Solution Approach 2:
The WAT equipment is enhanced to perform both DC electrical characteristic measurements and AC functional tests of static memory through the integration of the built-in self-test circuit. This multi-functional approach allows standard WAT equipment to replace specialized ATE equipment for memory functional testing.
2Device complexity
If WAT equipment is used for static memory test, then equipment cost is reduced, but AC test capability is lost and only DC characteristics can be measured
Solution Approach 1:
The static memory chip includes a built-in self-test circuit that autonomously generates AC test signals and performs functional testing, enabling standard DC-capable WAT equipment to conduct AC functional tests through the chip's internal circuitry without requiring the equipment itself to have AC test capabilities.
Solution Approach 2:
The built-in self-test circuit acts as an intermediary that translates simple DC voltage input from standard WAT equipment into complex AC test patterns, clock signals, and memory operations, thereby enabling functional testing through equipment that only provides DC voltage.
3Reliability
If custom-designed chips are used for memory functional test, then functional verification is achieved, but chip area increases and additional hardware is required
Solution Approach 1:
The test circuit functionality is merged with the normal memory array structure, sharing common components such as word lines, bit lines, sense amplifiers, and memory cells. This integration allows the same hardware to serve both as storage and as test equipment, eliminating the need for separate test chips or additional dedicated test hardware.
Solution Approach 2:
The memory array and its supporting circuitry are designed to serve dual purposes: normal memory operation and functional testing. The same memory cells, decoders, and sense amplifiers used for storage are also utilized for test pattern generation and evaluation, maximizing hardware utilization and minimizing area overhead.
Data Source
AI summary
The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.