SRAM Well Contact Layout for Low Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM devices face challenges in achieving low contact resistance for well contacts due to dopant segregation and limited doping optimization options, which restricts the integration density and performance.
Innovation Solution
The implementation of a comb-like well contact layout where well regions are electrically contacted at only one end, increasing the active area and reducing contact resistance, and the use of two types of edge cells to eliminate the need for insulation between P-well and N-well contacts, thereby reducing the contact area and optimizing doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional edge cells with both P-well and N-well contacts are used at column ends, then electrical connections to both wells are provided, but the contact resistance increases and active area is reduced due to insulation requirements
Solution Approach 1:
The patent divides the edge cell functionality into two separate specialized cells: one dedicated to N-well contact and another to P-well contact. This segmentation eliminates the need for insulation between contacts within the same edge cell, allowing each contact type to have its own optimized contact area without interference from the other well type, thereby reducing contact resistance and increasing active area.
Solution Approach 2:
The patent utilizes the column end position strategically, placing different well contact types at opposite ends of the column array. This spatial arrangement in the column dimension allows both N-well and P-well contacts to be provided without requiring insulation between them in the same location, effectively using dimensional separation to resolve the contact resistance and active area conflict.
2Reliability
If well regions are contacted at both ends of columns, then electrical connections are provided to both ends, but the layer footprint increases and integration density is limited
Solution Approach 1:
The patent extracts the N-well contact function and P-well contact function into separate specialized edge cells located at opposite column ends. This extraction eliminates the need for insulation structures between well contacts that would otherwise be required in conventional designs, reducing the layer footprint while maintaining all necessary electrical connections.
Solution Approach 2:
By utilizing the column end positions at opposite ends of the array, the patent effectively uses the column dimension to separate different well contact types. This dimensional approach allows both N-well and P-well contacts to be provided without overlapping in space, reducing the required layer footprint while maintaining complete electrical connectivity.
3Reliability
If insulation structures are added between P-well and N-well contacts in edge cells, then electrical insulation is provided, but device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
The patent removes the need for insulation structures by extracting the N-well and P-well contact functions into separate specialized edge cells. This elimination of insulation requirements directly reduces device structural complexity and simplifies the manufacturing process, while still providing the necessary electrical insulation between different well types through spatial separation.
Solution Approach 2:
The patent converts the potential harm of having both well types in the same edge cell (requiring complex insulation) into a benefit by placing them in separate specialized cells at column ends. This transformation eliminates the need for insulation structures entirely, simplifying the device structure and manufacturing while maintaining electrical isolation through physical separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the active area of P-well and N-well contacts while maintaining a small layer footprint, reducing contact resistance and improving integration density in highly scaled technologies.
Implementation Method 1
A P-type dopant may be implanted into the source and drain regions of the P-channel transistors
Implementation Method 2
Source and drain regions of the N-channel transistors may be doped with an N-type dopant
Implementation Method 3
electrical connections to the P-wells and N-wells may be provided, to which a body voltage of transistors formed in the P-well region and the N-well region is applied
Data Source
AI summary
A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.