SRAM Well Voltage Supply Cell Regularity via Asymmetric Gate Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In SRAM devices with multiple power supplies, it is challenging to arrange well voltage supply cells with the same regularity as surrounding memory cells, affecting the reliability and performance of the memory cells.
Innovation Solution
The arrangement of well voltage supply cells is achieved by incorporating a third gate electrode group symmetrically to a first gate electrode group of a first SRAM cell and a fourth gate electrode group symmetrically to a second gate electrode group of a second SRAM cell, with P-type and N-type impurity diffusion regions placed between them, allowing for regular placement and improved power supply management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple power supplies are provided in SRAM, then power consumption and cell operating margin are improved, but it becomes difficult to arrange well voltage supply cells with the same regularity as surrounding memory cells
Solution Approach 1:
The patent applies asymmetry by introducing a dummy gate electrode group that is asymmetric in position relative to the memory cell, while maintaining symmetric gate electrode groups (first and fourth, second and third) within each well voltage supply cell. This asymmetric dummy structure enables regular arrangement of well voltage supply cells alongside memory cells in the SRAM array, resolving the contradiction between providing multiple power supplies and maintaining arrangement regularity.
2Reliability
If well voltage supply cells are arranged with the same regularity as memory cells, then transistor characteristic fluctuations are reduced and reliability is enhanced, but the device structure becomes more complex
Solution Approach 1:
The patent applies universality by designing the well voltage supply cell to contain multiple gate electrode groups (first, second, third, and fourth) that can serve different functions: the first and second gate electrodes control access transistors, while the third and fourth gate electrodes control load transistors. This multi-functional structure within a single cell type enables both memory functionality and well voltage supply functionality, achieving regular arrangement without excessive structural complexity.
3Area of stationary object
If the size of well voltage supply cells is reduced, then the area of SRAM is reduced, but it becomes harder to maintain the same regularity as surrounding memory cells
Solution Approach 1:
The patent applies merging by combining the well voltage supply cell with memory cell functionality through the inclusion of multiple gate electrode groups within a single cell structure. The first and second gate electrodes function as access transistor gates, while the third and fourth gate electrodes function as load transistor gates, allowing the well voltage supply cell to serve dual purposes and be arranged regularly with memory cells while minimizing area overhead.
Data Source
AI summary
A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.