SRAM Memory Cell Wiring Layout for Accurate Resist Patterns

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Solution Overview

Problem

In semiconductor devices with SRAM memory cells, the dense arrangement of copper wirings leads to challenges in optical proximity correction, resulting in inaccurate resist patterns and improper filling of copper films, which can cause the SRAM memory cell to malfunction.

Innovation Solution

The semiconductor device design eliminates adjacent short first wirings and directly couples contact plugs to vias, allowing for improved optical proximity correction and accurate formation of desired wirings, thereby ensuring proper electrical couplings and functionality of the SRAM memory cell.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If copper wirings are formed by damascene technique in dense SRAM memory cell region, then interconnection functionality is achieved, but optical proximity correction cannot be made adequately resulting in inaccurate resist patterns

Engineering Contradiction:
Improveresist pattern accuracyVSAvoidwiring density
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the SRAM memory cell into six separate element formation regions (first through sixth), with each region containing specific transistors and their associated wirings. This segmentation allows each region to be formed independently with optimized wiring layouts, reducing the overall wiring density in any single region and enabling adequate optical proximity correction for each segment.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If wirings are arranged densely in SRAM memory cell region, then integration density is improved, but copper film cannot be properly filled in wiring trenches

Engineering Contradiction:
Improvewiring integration densityVSAvoidcopper filling accuracy
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

By segmenting the SRAM memory cell into six element formation regions, the patent distributes the wiring density across multiple regions rather than concentrating all wirings in a single dense region. This allows copper films to be properly filled in each region's wiring trenches while maintaining overall high integration density through efficient use of six regions.

Inventive Principle:
Principle #1Segmentation

3Length of moving object

If short first wirings are formed in dense arrangement, then wiring length is reduced, but optical proximity correction fails due to relation between adjacent wirings

Engineering Contradiction:
Improvewiring lengthVSAvoidoptical proximity correction accuracy
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent assigns different wiring length characteristics to different element formation regions. By distributing wirings across six segments, the patent can optimize wiring lengths in each region independently, ensuring that even short wirings can be formed with adequate optical proximity correction by spacing them appropriately within their respective segments.

Inventive Principle:
Principle #1Segmentation

4Manufacturing precision

If optical proximity correction is updated frequently to accommodate dense wiring patterns, then wiring formation accuracy is improved, but development time and costs increase

Engineering Contradiction:
Improvewiring formation accuracyVSAvoiddevelopment time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By dividing the SRAM memory cell into six element formation regions, the patent creates a wiring layout that is inherently more amenable to optical proximity correction. The segmented structure reduces the complexity of correction calculations and allows for more stable, long-term use of photo-mask patterns, thereby reducing the frequency of updates needed and lowering development time and costs.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9000503B2Semiconductor device
Publication Date: 2015.04.07 RENESAS ELECTRONICS CORP
  • US9000503B2 patent drawing
  • US9000503B2 patent drawing
  • US9000503B2 patent drawing

AI summary

A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.