SRAM Memory Macro Wiring Layout Noise Reduction
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Solution Overview
Problem
In semiconductor integrated circuit devices, the arrangement of passage wirings above memory macros can lead to noise-induced malfunctions due to parasitic capacitance, particularly affecting the symmetry of digit lines and the operation of sense amplifiers in SRAM macros.
Innovation Solution
A multilayer wiring structure is implemented, where passage wirings are arranged in specific layers to avoid extending over the column peripheral circuit, with certain wirings forbidden from extending in orthogonal directions above the memory cell array to minimize noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passage wirings are arranged above the column peripheral circuit for convenience of designing, then wiring layout flexibility is improved, but noise interference to digit lines increases causing malfunction
Solution Approach 1:
The patent extracts the harmful passage wirings from the area above the column peripheral circuit by prohibiting their arrangement there. Instead, passage wirings are redirected to extend only in the row direction above the memory cell array, separating them from the sensitive digit lines and sense amplifier circuits, thus eliminating noise interference while maintaining wiring functionality
Solution Approach 2:
The patent applies different wiring arrangement rules to different regions: above the memory cell array, passage wirings are permitted to extend in the row direction, while above the column peripheral circuit, passage wirings are prohibited. This localized quality control ensures wiring flexibility where needed while protecting sensitive areas from noise
2Quantity of substance
If passage wirings extend in parallel to digit line pairs above the memory cell array, then wiring density is improved, but symmetry of digit lines is lost causing sense amplifier malfunction
Solution Approach 1:
The patent deliberately introduces asymmetry in the wiring arrangement by prohibiting passage wirings from extending in the column direction (parallel to digit lines) above the memory cell array. This asymmetric restriction ensures that passage wirings do not create unequal parasitic capacitance effects on complementary digit lines, thereby maintaining digit line symmetry and sense amplifier functionality
3Adaptability or versatility
If passage wirings are arranged to transmit signals not supplied for memory macro, then design convenience is improved, but noise generation increases affecting digit lines
Solution Approach 1:
The patent uses the memory cell array region as an intermediary zone for passage wirings. By directing passage wirings to extend only in the row direction above the memory cell array (which contains only memory cells without sensitive readout circuitry), the patent allows signal transmission functionality while minimizing noise generation and interference to digit lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces malfunctions caused by noise and improves wiring quality by preventing passage wirings from being arranged above the column peripheral circuit, ensuring the stability and symmetry of digit lines in SRAM macros.
Implementation Method 1
there is a possibility of a malfunction of the memory macro due to noise... noise is generated on the digit line DTj due to a parasitic capacitance between the digit line DTj and the passage wiring 120-M
Data Source
AI summary
A semiconductor integrated circuit device includes a memory macro and M (M is an integer more than 1) passage wirings. The memory macro includes a memory cell array comprising memory cells which are arranged in a matrix, digit line pairs connected with the memory cells and extending in a column direction, and a column peripheral circuit connected with the digit line pairs and comprising a sense amplifier circuit. The M (M is an integer more than 1) passage wirings are arranged to extend in a row direction orthogonal to the digit line pairs. The arrangement of the M passage lines above the column peripheral circuit is forbidden.