SRAM Word-Line Enable Pulse Generator with Dynamic Delay
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Solution Overview
Problem
Static random access memories (SRAM) face challenges in maintaining the necessary time margin between bit line pre-charge and word-line enable times, especially in varying sizes of SRAMs, which affects data access and storage efficiency.
Innovation Solution
A word-line enable pulse generator is implemented with a delay unit and resistance unit to adjust the word-line enable time, using a high resistance wire to control the timing of the word-line enable pulse signal, ensuring the time margin requirement is met for both small and large size SRAMs by varying the resistance based on the number of word line drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the SRAM size is increased to improve storage capacity, then the time margin between bit line pre-charge and word-line enable times becomes difficult to maintain
Solution Approach 1:
The patent implements a dynamic delay time adjustment mechanism where the delay unit automatically adapts the word-line enable pulse timing based on the detected SRAM array size. The system transitions from static timing to dynamic timing adjustment, allowing the word-line enable time to be optimized for different SRAM configurations without manual intervention.
Solution Approach 2:
The patent employs a feedback mechanism where the system detects the actual SRAM array size and uses this information to adjust the delay time accordingly. The detection unit monitors the SRAM configuration and feeds this information back to the delay unit, which then modifies the word-line enable pulse timing to maintain proper time margins regardless of SRAM size.
2Manufacturing precision
If manual adjustment of word-line enable time is performed for each SRAM size, then timing accuracy is improved, but device complexity and adjustment time increase
Solution Approach 1:
The patent implements a self-service mechanism where the SRAM system automatically detects its own array size and adjusts its own timing parameters without external intervention. The delay unit autonomously configures the appropriate delay time based on detected SRAM characteristics, eliminating the need for manual timing adjustments and reducing system complexity.
Solution Approach 2:
The patent dynamically changes the delay time parameter based on detected SRAM array size. The system automatically modifies this critical timing parameter to match different SRAM configurations, achieving accurate timing without requiring complex manual adjustment procedures or multiple fixed configurations.
3Device complexity
If a fixed delay time is used for word-line enable pulse, then device complexity is reduced, but adaptability to different SRAM sizes deteriorates
Solution Approach 1:
The patent transforms the static delay time into a dynamic parameter that automatically adapts to different SRAM sizes. The delay unit responds to detected array dimensions by adjusting the delay time accordingly, providing versatility across different SRAM configurations while maintaining relatively simple circuit implementation through automated adjustment.
Solution Approach 2:
The patent creates a universal timing control mechanism that can serve multiple SRAM sizes and configurations through a single delay unit. This unified approach eliminates the need for separate timing circuits for different SRAM sizes, achieving multi-functionality while keeping the overall device complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures efficient data access and storage by maintaining the required time margin between bit line pre-charge and word-line enable times, reducing the need for manual adjustments and improving SRAM performance across different sizes.
Implementation Method 1
A delay unit is configured to delay a word-line enable pulse signal to be provided to a plurality of word line drivers of the SRAM. The delay unit includes a first transistor coupled between the plurality of word line drivers of the SRAM and a first power source, a resistance unit coupled between the first transistor and a second power source that is different from the first power source
Data Source
AI summary
A word-line enable pulse generator for a SRAM is provided. The word-line enable pulse generator includes a delay unit. The delay unit is configured to delay a word-line enable pulse signal to be provided to a plurality of word line drivers of the SRAM. The delay unit includes a first transistor coupled between the plurality of word line drivers of the SRAM and a first power source, a resistance unit coupled between the first transistor and a second power source that is different from the first power source, and a second transistor coupled between the first transistor and the resistance unit. The first transistor has a gate for receiving an enable signal. The second transistor has a gate for receiving the enable signal. An edge of the word-line enable pulse signal is delayed from the enable signal by a delay time corresponding to a resistance of the resistance unit.