SRAM Word Line Underdrive for Multi-Row In-Memory Compute
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Solution Overview
Problem
Existing in-memory computation circuits using standard SRAM cells face data flip issues during simultaneous access of multiple rows, leading to accuracy loss and performance degradation, particularly due to fixed word line underdrive solutions that compromise read current variability.
Innovation Solution
Implementing an adaptive word line underdrive control system that adjusts the supply voltage based on integrated circuit process and temperature conditions, using a voltage generator circuit to generate an adaptive supply voltage for the word line driver circuits, ensuring optimal underdrive levels for each operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed word line underdrive voltage is applied to all process corners, then data flip is prevented, but read current variability increases leading to accuracy loss
Solution Approach 1:
The patent implements dynamic word line underdrive voltage adjustment based on process corner detection. The system transitions from a fixed underdrive voltage applied to all process corners to a dynamic voltage selection mechanism that adapts the underdrive level according to the detected process corner (fast, slow, or nominal), thereby preventing data flips while minimizing read current variability
Solution Approach 2:
The patent changes the voltage parameter of the word line underdrive based on process conditions. By detecting the process corner and selecting appropriate underdrive voltage levels (Vud_fast, Vud_slow, or Vud_nominal), the system optimizes the electrical parameters to prevent data flips in fast corners while maintaining read current stability across all process variations
2Reliability
If word line underdrive is increased to prevent data flips, then reliability improves, but computation performance degrades
Solution Approach 1:
The patent adjusts the word line underdrive voltage parameter dynamically based on process corner detection. Instead of applying a uniformly high underdrive voltage that degrades performance, the system selects appropriate underdrive levels (higher for fast corners to prevent data flips, lower for slow corners to maintain performance), thereby optimizing both reliability and computation performance
3Area of stationary object
If standard SRAM cells are used without specialized design, then circuit area is minimized, but data flip occurs during simultaneous row access
Solution Approach 1:
The patent introduces an intermediary process corner detection circuit and voltage selection mechanism between the standard SRAM cells and the word line driver. This intermediary system detects the process corner and selects appropriate underdrive voltages to prevent data flips during simultaneous row access, allowing the use of standard SRAM cells without specialized design modifications while maintaining data stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adaptive word line underdrive control enhances data accuracy and computation performance by minimizing data flips and read current variability, while maintaining the advantages of standard SRAM cells without increasing circuit area.
Implementation Method 1
an adaptive supply voltage having a level which is dependent on integrated circuit process and/or temperature conditions
Implementation Method 2
said adaptive supply voltage having a level which is dependent on integrated circuit process and/or temperature conditions
Data Source
AI summary
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.