SRAM Word Line Voltage Boosting for Unique ID Generation
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges in generating a unique ID that is secure and efficient, as previous methods require overhead in power supply voltage control and may involve time-consuming memory tests or complex bit line operations, which can lead to data falsification or cloning risks.
Innovation Solution
A method is introduced where a boosted voltage is applied to the word line of an SRAM memory cell, exceeding the power supply voltage, and then lowered, causing the memory cell to enter an undefined state, allowing it to hold data based on manufacturing variations, thereby generating a unique ID with reduced overhead and enhanced security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory test is performed to generate a unique ID using manufacturing variations, then a secure unique ID can be obtained, but it requires overhead in power supply voltage control and time-consuming operations
Solution Approach 1:
The patent applies preliminary action by pre-establishing the manufacturing variations in the SRAM memory cells during the semiconductor fabrication process. These variations are inherently present before any ID generation operation, allowing the system to quickly exploit these pre-existing differences without requiring time-consuming setup or calibration procedures during ID generation.
Solution Approach 2:
The patent utilizes parameter changes by varying the power supply voltage to the SRAM memory cells during the ID generation process. By changing the voltage parameters, the system can read the manufacturing variations embedded in the memory cells and convert these physical differences into a unique digital ID, achieving both security and speed.
2Reliability
If a memory test is performed to generate a unique ID, then a secure unique ID can be obtained, but it requires complex overhead in power supply voltage control and bit line operations
Solution Approach 1:
The patent applies universality by designing the SRAM memory cells to serve dual purposes: normal memory storage operations and unique ID generation. The same memory cell array and basic circuitry are used for both functions, eliminating the need for separate dedicated hardware for ID generation and reducing overall system complexity.
Solution Approach 2:
The patent implements self-service by allowing the SRAM memory cells to automatically reveal their unique manufacturing characteristics when subjected to specific voltage conditions. The physical variations in the memory cells themselves perform the ID generation function without requiring external calibration or complex control mechanisms, making the process inherently simpler.
3Ease of manufacture
If data is stored in the semiconductor chip at the time of manufacture, then an ID can be provided, but there is a risk that the data is falsified or the chip is cloned
Solution Approach 1:
The patent applies local quality by focusing on the unique physical characteristics of individual memory cells rather than relying on globally stored data. Each memory cell has slightly different manufacturing variations at the local level, and these local differences are exploited to generate a unique ID that is inherently difficult to replicate or falsify.
Solution Approach 2:
The patent converts the harm of manufacturing variations (which traditionally cause yield losses and defective chips) into a beneficial feature. Instead of discarding chips with non-uniform memory cell characteristics, the invention exploits these variations as the foundation for generating unique, unclonable IDs, turning a manufacturing challenge into a security advantage.
Data Source
AI summary
There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.