Shared Word Line Pull-Down Circuit for SRAM Read Assist
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reliability of Static Noise Margin (SNM) in SRAM devices is deteriorating, and existing read assist techniques, such as lowering word line voltage, require additional transistors, increasing the WL driver area and causing performance penalties.
Innovation Solution
A new structural circuit is introduced that allows pull down circuits to be shared between adjacent word lines, reducing the area and loading of these circuits, and utilizing transistors to adjust word line voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional transistors are added to lower word line voltage for read assist, then read assist capability is improved, but WL driver area increases
Solution Approach 1:
The patent merges the pull-down circuit functionality across multiple word lines by sharing common transistors (PM1-PM4) between adjacent word lines. Instead of dedicating separate pull-down circuits to each word line, the invention combines resources so that transistors can be controlled to serve multiple word lines sequentially, thereby reducing the total transistor count and WL driver area while maintaining read assist capability.
Solution Approach 2:
The shared pull-down circuit transistors are designed to perform multiple functions by being controlled through different control signals (RA1, RA2) for different word lines. The same physical transistors can lower voltage for different word lines at different times, making the circuit universal and multi-functional rather than dedicated to a single word line.
2Reliability
If additional transistors are added to lower word line voltage for read assist, then read assist capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the pull-down circuit functionality across multiple word lines by sharing common transistors (PM1-PM4) between adjacent word lines. Instead of dedicating separate pull-down circuits to each word line, the invention combines resources so that transistors can be controlled to serve multiple word lines sequentially, thereby reducing the total transistor count and WL driver area while maintaining read assist capability.
3Area of stationary object
If pull down circuits are shared between adjacent word lines, then area is reduced, but control complexity increases
Solution Approach 1:
The control is segmented into distinct control signals (RA1, RA2) for different word lines. Each control signal independently manages the shared transistors for its associated word line, allowing the control logic to be divided into manageable segments rather than requiring a single complex control unit. This segmentation reduces control complexity while enabling area reduction through sharing.
Data Source
AI summary
A memory device is provided, including a first word line coupled to a first memory cell, a second word line coupled to a second memory cell, and a read assist circuit coupled between the first and second word lines, and in a first time period configured, in response to a first control signal, to adjust a voltage level of the first word line to a first voltage and to adjust a voltage level of the second word line to a second voltage. In some embodiments, the first voltage is smaller than a first supply voltage, and the second voltage is greater than a second supply voltage smaller than the first supply voltage.