SRAM Word Line Pulse Width Control for Lower Power
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Solution Overview
Problem
Existing timing tracking techniques for SRAM devices result in significant power wastage due to all word lines sharing the same tracking scheme, leading to inefficient power consumption, especially for bit cells farther from the controller.
Innovation Solution
A memory device with a controller that adjusts the pulse width of word line signals based on the physical distance from the controller, using tracking columns and dummy cells to emulate signal routing delays, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all word lines share the same tracking scheme, then timing tracking is simplified, but power consumption increases significantly
Solution Approach 1:
The patent divides the word lines into multiple groups based on their physical distance from the controller. Each group is assigned a different pulse width parameter, allowing differentiated timing tracking for different segments of the memory array. This segmentation resolves the contradiction by maintaining simple tracking within each segment while avoiding uniform tracking across the entire array, thereby reducing unnecessary power consumption.
Solution Approach 2:
The patent applies different pulse widths to different regions of the memory array based on their local characteristics (distance from controller). Word lines closer to the controller receive shorter pulse widths, while those farther away receive longer pulse widths. This local quality approach allows optimized power consumption in each region without complicating the overall tracking mechanism.
2Ease of operation
If fixed pulse width is used for all word lines, then control is simplified, but power wastage increases for distant bit cells
Solution Approach 1:
The patent introduces dynamic pulse width adjustment based on the physical location of word lines. Instead of a fixed pulse width, the system dynamically selects pulse widths from a set of predetermined values corresponding to different distance ranges. This dynamic approach reduces power wastage for distant bit cells while maintaining ease of operation through automated selection based on address signals.
Solution Approach 2:
The patent changes the pulse width parameter based on the physical distance parameter of word lines from the controller. By mapping distance ranges to specific pulse width values, the system optimizes power consumption without complex control mechanisms. This parameter change approach allows the system to adapt to different operational conditions automatically.
3Reliability
If longer pulse width is used for all word lines, then distant bit cells are adequately activated, but power consumption increases
Solution Approach 1:
The patent applies partial action by using longer pulse widths only for the subset of word lines that require them (those farther from the controller). Closer word lines receive shorter pulse widths that are sufficient for their activation. This partial application of excessive action avoids unnecessary energy consumption while ensuring reliable activation where needed.
Data Source
AI summary
A memory device includes a memory array including a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells, and a controller operatively coupled to the memory array. The controller is configured to receive a first address signal indicating a first word line that is physically arranged with respect to the controller by a first distance, assert the first word line through a first signal with a first pulse width, receive a second address signal indicating a second word line that is physically arranged with respect to the controller by a second distance, assert the second word line through a second signal with a second pulse width, and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.