SRAM Wordline Pulse Width Adjustment for Neural Network Power Optimization
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Solution Overview
Problem
Prior art SRAMs do not provide flexibility in trading off memory access time with data accuracy and power consumption, particularly in neural network applications where high order bits are critical and low order bits can be corrupted without affecting inference accuracy, leading to higher power consumption.
Innovation Solution
A static random access memory (SRAM) design that modifies the wordline signal pulse width to achieve specific error rates, allowing for a shorter path length for most significant bits and longer paths for less significant bits, enabling adjustable error rates from 2% to nearly error-free, thereby optimizing power consumption and memory speed based on error tolerance requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the wordline signal pulse width is shortened to reduce power consumption, then power consumption is reduced, but data accuracy deteriorates due to increased error rates
Solution Approach 1:
The patent applies local quality by differentiating the wordline pulse width allocation for different bit positions. Most significant bits (MSBs) are assigned shorter pulse widths corresponding to shorter wordline paths, while least significant bits (LSBs) are assigned longer pulse widths corresponding to longer wordline paths. This localized differentiation allows each bit to receive appropriate activation time based on its specific path requirements, reducing overall power consumption while maintaining data accuracy for critical bits.
Solution Approach 2:
The patent segments the memory word into different bit significance groups (MSBs and LSBs) and applies different wordline pulse width settings to each segment. This segmentation allows independent optimization of pulse widths for different bit positions, enabling the system to reduce power consumption by using minimum necessary pulse widths for MSBs while providing sufficient pulse widths for LSBs that can tolerate longer activation times.
2Quantity of substance
If the wordline signal path length is increased to accommodate more memory cells, then memory capacity is increased, but access time increases due to longer signal propagation
Solution Approach 1:
The patent applies dynamics by making the wordline pulse width dynamic and adjustable based on the specific memory cell address being accessed. Rather than using a fixed conservative pulse width for all cells, the system dynamically selects appropriate pulse widths from multiple settings (e.g., first, second, third pulse widths) based on the wordline path length required for the target memory cell, optimizing both speed and power consumption for each access operation.
Solution Approach 2:
The patent changes the parameter of wordline pulse width based on the memory cell location and path length. By having multiple configurable pulse width settings and selecting the appropriate one based on the target cell's distance from the controller, the system optimizes access time for each specific memory location while maintaining the ability to access the full memory capacity.
3Manufacturing precision
If the wordline signal pulse width is increased to improve data accuracy, then data accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by providing just enough wordline pulse width for each bit position to achieve acceptable error rates, rather than uniformly applying excessive pulse widths to all bits. MSBs receive minimum necessary pulse widths (first, second, or third pulse widths) sufficient for their shorter paths, while LSBs receive longer pulse widths only when needed, avoiding unnecessary energy consumption from excessive activation times on all bits.
Data Source
AI summary
A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable wordline signal pulse width which may be reduced sufficiently to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and a nearly error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline signal pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline signal pulse width with an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.