Configurable Wordline Voltage for SRAM Stability
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Solution Overview
Problem
As technology scales, static random access memory (SRAM) cell variation becomes increasingly problematic, making it difficult to balance read stability and writeability, leading to reduced yields due to process variations that affect dopant levels and device threshold voltages, causing SRAM cells to be unstable or unwriteable.
Innovation Solution
An Array Built In Self Test (ABIST) method and circuit that uses configurable wordline voltage levels to adjust the beta ratio of pass gate to pulldown device current, improving SRAM stability and chip yields by selectively adjusting the wordline voltage levels during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process variation occurs during manufacturing, then device threshold voltages and dopant levels vary, but SRAM cell stability and writeability deteriorate
Solution Approach 1:
The patent applies parameter changes by adjusting the wordline voltage level to compensate for process variations. Multiple wordline voltage levels are provided, and the appropriate level is selected based on the actual SRAM cell characteristics to restore stability and writeability affected by manufacturing variations in dopant levels and threshold voltages.
2Reliability
If pass gate voltage threshold decreases due to process variation, then pass gate becomes stronger, but beta ratio skew increases causing instability
Solution Approach 1:
The patent changes the wordline voltage parameter to compensate for beta ratio skew caused by process variation. By providing multiple wordline voltage levels, the system can select an appropriate voltage that corrects the imbalanced beta ratio between pass gate and pulldown device, restoring proper SRAM cell stability.
3Reliability
If configurable wordline voltage levels are implemented, then SRAM stability and chip yield improve, but device complexity increases
Solution Approach 1:
The patent implements dynamics by providing configurable wordline voltage levels that can be adjusted based on actual SRAM cell characteristics. The wordline voltage is not fixed but can be dynamically selected from multiple levels to optimize stability and writeability for each cell or block, improving yield despite increased complexity.
Solution Approach 2:
The patent applies local quality by allowing different wordline voltage levels to be applied to different SRAM cells or blocks based on their individual characteristics. This localized adjustment enables each region to be optimized for its specific process variation, improving overall chip yield while managing complexity through selective configuration.
Data Source
AI summary
An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.