SRAM Transistor Work Function Layer Optimization
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Solution Overview
Problem
The electrical performance of SRAMs in semiconductor devices formed by conventional methods needs to be improved to enhance the read margin and overall performance of memory devices.
Innovation Solution
A semiconductor device fabrication method involving a base substrate with N-type and P-type logic regions, PD transistor regions, and PG transistor regions, where specific work function layers are formed with varying thicknesses and materials to optimize the threshold voltages and beta ratio of transistors, thereby improving the open-state current and read margin of SRAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used, then manufacturing process is simple, but electrical performance of SRAM is insufficient
Solution Approach 1:
The patent applies local quality by forming different work function layer structures in different transistor regions. Specifically, the first work function layer is formed in the first transistor region while the second work function layer is formed in the second transistor region, allowing each region to have optimized electrical characteristics tailored to its specific function within the SRAM device.
Solution Approach 2:
The patent implements parameter changes by varying the work function layer configuration across different transistor regions. The first and second work function layers have different material compositions, thicknesses, and formation conditions, which directly alter the threshold voltage and electrical performance parameters of the transistors in respective regions, thereby improving overall SRAM electrical performance.
2Reliability
If work function layers with different thicknesses are formed, then beta ratio and read margin improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the work function layer formation into distinct segments: a first work function layer formed in the first transistor region and a second work function layer formed in the second transistor region. This segmentation allows independent optimization of each layer's thickness and material properties, achieving the required beta ratio and read margin while managing manufacturing precision through region-specific control.
Solution Approach 2:
The patent implements local quality by tailoring the work function layer characteristics to specific regional requirements within the SRAM device. The first and second work function layers are formed with different properties suited to their respective transistor regions, enabling precise control of local electrical characteristics to achieve target read margin and beta ratio performance.
3Reliability
If multiple work function layers are formed with different materials, then transistor threshold voltages are optimized, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming different work function layer structures in different transistor regions. Specifically, the first work function layer is formed in the first transistor region while the second work function layer is formed in the second transistor region, allowing each region to have optimized electrical characteristics tailored to its specific function within the SRAM device.
Solution Approach 2:
The patent implements composite materials by using different material compositions for the first and second work function layers. This allows the device to utilize the advantageous properties of multiple materials in different regions, optimizing threshold voltages and electrical performance through strategic material selection and combination.
Data Source
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AI summary
A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an N-type logic region, a P-type logic region, a first pull down transistor (PDT) region, a second PDT region, and a pass gate transistor (PGT) region, forming a first work function layer (WFL) in the first N-type threshold-voltage (TV) region, the P-type logic region, the second PDT region, and the PGT region, forming a second WFL on the first WFL in the first P-type TV region, and forming a third WFL on the second WFL in the first P-type TV region, the first WFL in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PDT region. The thickness of the third WFL is smaller than the thickness of the first WFL. The method further includes forming a fourth WFL on the substrate.