SRAM Work Function Layer Segmentation for Parameter Matching
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Solution Overview
Problem
Conventional SRAM devices face challenges in achieving improved electrical performance due to mismatched electrical parameters between P-type and N-type transistors, primarily caused by diffusion and interaction of work function (WF) layers at their interface, which affects threshold voltages and overall device performance.
Innovation Solution
A method for fabricating SRAM devices involves forming a base substrate with distinct WF layers in the P-type and N-type transistor regions, including a P-type WF layer, a second P-type WF layer, and an N-type WF layer, with the N-type layer extending onto the sidewalls and top surface of the P-type layers, to simplify the WF layer interface and reduce inter-diffusion, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional WF layers are formed in both PU and PD transistor regions, then the fabrication process is simplified, but electrical parameter mismatch occurs due to diffusion and interaction at the interface
Solution Approach 1:
The patent segments the WF layer configuration into two distinct regions: the PU transistor region maintains a conventional dual-layer WF structure (first WF layer on gate dielectric, second WF layer on first WF layer), while the PD transistor region uses only a single-layer WF structure (first WF layer on gate dielectric with the second WF layer removed). This segmentation allows each region to have optimized electrical characteristics while simplifying the overall fabrication process by using a unified deposition sequence followed by selective removal in the PD region.
2Reliability
If WF layers are removed from the PD transistor region, then electrical parameter mismatch is reduced, but additional fabrication steps are required
Solution Approach 1:
The patent applies preliminary action by forming both the first WF layer and the second WF layer across the entire gate structure (both PU and PD transistor regions) before any selective removal. This preliminary formation ensures uniform deposition and establishes a baseline structure, after which the second WF layer is selectively removed only in the PD transistor region. This approach simplifies process control compared to attempting to form WF layers selectively from the beginning.
3Reliability
If a simple WF layer interface is formed, then inter-diffusion is reduced, but the structure requires precise layer removal and formation sequences
Solution Approach 1:
The first WF layer serves as an intermediary layer that remains in both PU and PD transistor regions, providing a common foundation. The second WF layer is deposited on top of the first WF layer in the PU region but is selectively removed in the PD region. This intermediary structure allows for precise control of the interface: in the PU region, both layers are present for optimal electrical characteristics, while in the PD region, only the first WF layer remains, creating a simplified interface with reduced inter-diffusion risk.
Data Source
AI summary
A static random-access memory (SRAM) device includes a base substrate including a PU transistor region and a PD transistor region adjacent to the PU transistor region, a gate dielectric layer formed on a portion of the base substrate in the PU transistor region and the PD transistor region, a first WF layer formed on a portion of the gate dielectric layer in the PU transistor region and a second WF layer formed on the first WF layer in the PU transistor region, and a third WF layer formed on a top surface and a sidewall surface of the second WF layer in the PU transistor region, a sidewall surface of the first WF layer in the PU transistor region, and the gate dielectric layer in the PD transistor region. Each of the first WF layer and the second WF layer is made of a P-type WF material, and the third WF layer is made of an N-type WF material. The SRAM device also includes a gate electrode layer formed on the third WF layer.