SRAM Work Function Regulation Layer Segmentation
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Solution Overview
Problem
In vertical Gate-All-Around (GAA) nanowire SRAMs, metal diffusion between P-type and N-type work function regulation layers leads to transistor mismatch, affecting the performance and yield of SRAM devices.
Innovation Solution
A SRAM device design with a substrate featuring separated semiconductor columns for Pull-Up and Pull-Down transistors, including a gate stack structure with distinct P-type and N-type work function regulation layers, and a separation region to mitigate metal diffusion, along with a manufacturing method that forms these layers to prevent mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type and N-type work function regulation layers are placed adjacent to each other for gate structure adjustment, then transistor performance is improved, but metal diffusion occurs between the layers causing transistor mismatch
Solution Approach 1:
The patent introduces a separation region that divides the P-type and N-type work function regulation layers into distinct areas. This segmentation prevents direct contact between the two layers, thereby eliminating metal diffusion while maintaining their individual functions for transistor performance optimization.
Solution Approach 2:
The separation region acts as an intermediary barrier between the P-type and N-type work function regulation layers. This intermediate structure prevents harmful metal diffusion while allowing both layers to maintain their respective work function adjustment capabilities, thus resolving the contradiction between performance improvement and manufacturing precision.
2Ease of manufacture
If work function regulation layers are used to adjust gate structures, then transistor characteristics are optimized, but metal diffusion between layers causes yield reduction
Solution Approach 1:
By segmenting the work function regulation layers with a separation region, the patent enables independent optimization of P-type and N-type transistor characteristics without the harmful side effect of metal diffusion, thus maintaining ease of manufacture while improving productivity.
Solution Approach 2:
The separation region serves as a protective intermediary that allows the work function regulation layers to perform their gate structure adjustment function while preventing metal diffusion that would otherwise reduce SRAM yield.
3Reliability
If metallic elements are used in work function regulation layers for gate adjustment, then transistor performance is enhanced, but mutual diffusion between P-type and N-type layers occurs
Solution Approach 1:
The separation region segments the P-type and N-type work function regulation layers, physically isolating the metallic elements in each layer. This segmentation maintains the composition stability of each layer while preserving the performance-enhancing properties of the metallic elements.
Solution Approach 2:
The separation region acts as a stabilizing intermediary that prevents mutual diffusion between metallic elements in P-type and N-type layers, thereby maintaining composition stability while allowing each layer to independently optimize transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces transistor mismatch by preventing metal diffusion between the work function regulation layers, enhancing the performance and yield of SRAM devices.
Implementation Method 1
a first separation region on the substrate between the first and the second semiconductor columns
Data Source
AI summary
A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.