SRAM Gate Work Function Tuning for Density and Leakage Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Deep sub-micron SRAM design faces challenges due to process variations leading to cell mismatch issues, which affect memory density and performance in semiconductor chips.
Innovation Solution
The implementation of different types of SRAM memory cells with varying designs, including single-fin-line FinFETs, to achieve high density and low standby leakage, with specific work function layers and gate structures optimizing threshold voltages for each type, allowing for high-density and high-speed memory operations in a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process variations are reduced to improve manufacturing precision, then cell mismatch issues are reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies parameter changes by adjusting the work function of gate electrodes through selective material composition (e.g., different metal layers with specific work functions) and gate structure dimensions. This allows optimization of threshold voltages for different SRAM cell types without requiring tighter process control, thereby reducing cell mismatch issues while avoiding increased manufacturing complexity
Solution Approach 2:
The patent implements local quality by providing different gate electrode structures and work function layers for different SRAM cell types (e.g., first type vs. second type cells) within the same memory device. This enables each cell type to have locally optimized parameters tailored to its specific function, improving overall manufacturing precision without uniform process complexity increases
2Quantity of substance
If SRAM cell area is reduced to increase memory density, then more cells fit on chip, but cell performance and reliability deteriorate
Solution Approach 1:
The patent uses parameter changes by optimizing the gate electrode work function and channel dimensions to maintain reliable cell operation at reduced sizes. By carefully selecting gate materials and adjusting threshold voltages, the patent achieves high memory density while preserving cell performance and reliability even as cell area shrinks
Solution Approach 2:
The patent applies local quality by providing different gate structures and work function configurations for different cell types in high-density regions. This allows each cell to have locally optimized parameters that ensure reliable operation despite the overall reduction in cell area, thereby maintaining reliability while increasing memory density
3Speed
If threshold voltage is optimized for high-speed operation, then data access speed improves, but standby leakage increases
Solution Approach 1:
The patent applies parameter changes by using different gate electrode work functions and channel dimensions to create SRAM cells with different threshold voltage characteristics. This enables optimization of data access speed for frequently accessed data while maintaining lower standby leakage for less frequently accessed data, effectively managing the speed-leakage tradeoff through parameter variation
Data Source
AI summary
An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.