SRAM Write Assist Circuit With Address-Based Negative Bitline Bias
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Solution Overview
Problem
SRAM cells experience issues with high IR voltage drops and process variations, leading to degraded memory write operations, especially in advanced process technologies and dense arrays, due to parasitic resistance and capacitance in bitlines.
Innovation Solution
A write assist circuit that includes a control circuit, voltage generator, and pull-down device to provide reference voltages that compensate for weaker NMOS pass devices and bitline parasitic resistance by adjusting voltages based on memory cell location, using capacitive elements to generate negative voltages and optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM arrays are made denser with more memory cells, then storage capacity increases, but IR voltage drops and process variations worsen
Solution Approach 1:
The patent applies local quality by providing different reference voltages to different portions of the SRAM array based on their specific needs. The write assist circuit generates multiple reference voltages (e.g., first reference voltage for first portion, second reference voltage for second portion) tailored to compensate for local variations in parasitic resistance and process conditions, thereby maintaining write reliability across the entire dense array without sacrificing storage capacity.
2Reliability
If write driver strength is increased to overcome parasitic resistance, then write reliability improves, but power consumption increases
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting reference voltage levels based on the specific write operation requirements and memory cell location. Instead of using a fixed high-strength write driver that consumes excessive power, the circuit selects appropriate reference voltages (e.g., higher voltage for cells with higher parasitic resistance, lower voltage for cells with lower resistance) to achieve reliable writes with optimized power consumption.
3Speed
If process technology is advanced to increase speed, then data access speed improves, but IR voltage drops and process variations increase
Solution Approach 1:
The patent implements feedback by using write assist circuits that sense and compensate for process variations and IR voltage drops in real-time. The circuit monitors write operation conditions and adjusts reference voltages accordingly, providing negative feedback to counteract the worsening effects of advanced process technology variations and maintain both high speed and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The write assist circuit enhances memory write operations by reducing IR voltage drops and process variation effects, improving data integrity and reducing power consumption across different portions of the SRAM array.
Implementation Method 1
the first capacitive element is configured to couple the reference voltage to a first negative voltage; the first and second capacitive elements are configured to cumulatively couple the reference voltage to a second negative voltage
Data Source
AI summary
A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.