SRAM Write Assist Circuit for Bitline IR Drop Compensation
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Solution Overview
Problem
Static Random Access Memory (SRAM) faces challenges in maintaining high-speed data access and accurate memory write operations due to IR voltage drops across bitlines, which degrade the performance of SRAM cells, especially those farther from the write driver circuit, and process variations in transistor strengths.
Innovation Solution
The implementation of a write assist circuit that includes a control circuit and a voltage generator, which provides a reference voltage and adjusts it to compensate for parasitic elements and process variations by cumulatively coupling it to different negative voltages based on memory address information, using capacitive elements to optimize bitline voltages and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the SRAM array is expanded to increase memory capacity, then the memory capacity is improved, but the IR voltage drop increases causing write operations to fail for cells farther from the write driver
Solution Approach 1:
The patent introduces a write assist circuit as an intermediary component between the write driver and memory cells. This circuit includes a voltage generator that produces adjusted bitline voltages and transfer gates that conditionally apply these voltages based on write enable signals, thereby compensating for IR voltage drops in expanded SRAM arrays
Solution Approach 2:
The patent dynamically changes the bitline voltage parameter based on the distance from the write driver. The voltage generator adjusts the bitline voltage to be higher for memory cells farther away, compensating for the increased IR voltage drop. This is achieved through controlled coupling of negative voltages to the reference voltage based on memory address information
2Reliability
If the write driver provides high voltage to ensure accurate writes to distant cells, then write accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different regions of the SRAM array based on their distance from the write driver. The write assist circuit selectively adjusts bitline voltages for specific memory cells or regions that require it, rather than uniformly increasing voltage across the entire array, thereby reducing overall power consumption while maintaining write accuracy where needed
Solution Approach 2:
The patent dynamically adjusts bitline voltages based on real-time conditions including memory address information and write enable signals. The transfer gates conditionally connect the voltage generator output to bitlines only when writing to distant cells, making the power consumption adaptive to the actual write operation requirements
3Ease of manufacture
If process variations cause transistor strength differences, then manufacturing cost is reduced, but write operation reliability deteriorates
Solution Approach 1:
The patent incorporates feedback mechanisms where the write assist circuit monitors write operation outcomes and adjusts subsequent write voltages accordingly. The circuit uses memory address information to determine which cells require voltage compensation and adjusts the bitline voltage in response to detected variations, ensuring reliable writes despite process variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The write assist circuit effectively compensates for IR voltage drops and process variations, ensuring accurate memory write operations and reducing power consumption by optimizing voltage levels across the SRAM array, particularly for cells farther from the write driver and in different portions of the array.
Implementation Method 1
the first capacitive element is configured to couple the reference voltage to a first negative voltage... the first and second capacitive elements are configured to cumulatively couple the reference voltage to a second negative voltage
Data Source
AI summary
The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.