SRAM Write Assist Circuit for Bitline IR Drop Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Static Random Access Memory (SRAM) faces challenges in maintaining accurate data write operations due to IR voltage drops across bitlines, which degrade performance as bitline parasitic resistance increases with advancing process technologies and density, leading to unintended voltage rises at memory cells farther from the write driver circuit.
Innovation Solution
The implementation of a write assist circuit that includes a control circuit and voltage generator, which provides reference voltages to bitlines, compensating for IR drops by adjusting voltages based on memory address information and partitioning SRAM arrays into portions to optimize voltage levels and reduce power consumption, using auxiliary bitlines to decrease parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM density is increased using advancing process technologies, then storage capacity is improved, but bitline parasitic resistance increases causing IR voltage drops
Solution Approach 1:
The bitline is segmented into multiple sections with separate write drivers for different portions of the SRAM array. This segmentation allows each write driver to serve a localized region, reducing the effective bitline length and parasitic resistance that each driver must overcome, thereby mitigating IR voltage drops while maintaining high density
Solution Approach 2:
A voltage compensation circuit acts as an intermediary between the write driver and the memory cell. This intermediary circuit dynamically adjusts and compensates for the IR voltage drop by providing additional voltage headroom to the bitline, ensuring that sufficient write voltage reaches distant cells despite increased parasitic resistance from high density
2Area of stationary object
If bitline length is increased to access farther memory cells, then array coverage is improved, but voltage accuracy degrades due to IR drops
Solution Approach 1:
The SRAM array is divided into multiple regions, each with its own write driver and bitline segment. This segmentation ensures that no single bitline becomes excessively long, maintaining voltage accuracy across all memory cells while achieving comprehensive array coverage through distributed write drivers
Solution Approach 2:
The write assist circuit dynamically changes voltage parameters by providing adjustable compensation voltages to counteract IR drops. This allows the system to maintain accurate write voltages across varying bitline lengths, enabling access to distant memory cells without sacrificing voltage precision
3Reliability
If write voltage is increased to overcome IR drops, then write reliability is improved, but power consumption increases
Solution Approach 1:
Voltage compensation is applied locally and selectively to only those bitline segments experiencing significant IR drops. Rather than uniformly increasing write voltage across the entire array, the system provides targeted compensation only where needed, maintaining write reliability in affected regions while minimizing unnecessary power consumption in regions with adequate voltage headroom
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The write assist circuit effectively compensates for IR voltage drops and process variations, ensuring accurate data writes across SRAM cells by adjusting voltages and reducing power consumption through negative voltage tuning, improving SRAM performance and efficiency.
Implementation Method 1
the first capacitive element is configured to couple the reference voltage to a first negative voltage; the first and second capacitive elements are configured to cumulatively couple the reference voltage to a second negative voltage
Data Source
AI summary
A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.