Write Assist Circuit for SRAM Voltage Reduction and Bit Line Coupling
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Solution Overview
Problem
Existing write assist schemes for SRAM cells consume excessive IC area and power, and can lead to performance degradation and increased costs due to high voltage requirements.
Innovation Solution
A write assist architecture that combines a drain supply voltage lowering circuit with a negative bit line boost circuit, using a capacitor and transistor configuration to reduce power consumption and voltage stress, allowing operation at lower voltages while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write assist schemes are used, then write margin issues are addressed, but IC area and power consumption increase
Solution Approach 1:
The patent combines the Vdd lowering circuit and negative bit line boost circuit into a single integrated write assist architecture. The capacitor is shared between both functions, and the transistor networks are merged to provide both voltage reduction and bit line driving capabilities simultaneously, reducing overall circuit area and power consumption compared to separate implementations.
Solution Approach 2:
The patent dynamically changes the supply voltage parameter by lowering Vdd to a reduced voltage level (Vdd') during write operations. This parameter change enables the circuit to achieve write margin improvement through voltage stress modulation while reducing power consumption by operating at lower voltage levels when full Vdd is not required.
2Reliability
If high voltage is used to address write margin issues, then write reliability improves, but device stress and power consumption increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the supply voltage to a reduced level (Vdd') during write operations. This allows the circuit to apply controlled voltage stress to improve write margin while avoiding the excessive voltage stress and power consumption associated with conventional high-voltage write assist schemes.
Solution Approach 2:
The patent introduces an intermediary capacitor that couples the lowered supply voltage to the bit line circuitry. This capacitor acts as a mediator that enables voltage transition and stress application without requiring sustained high voltage, thereby improving write margin while reducing overall voltage stress and power consumption.
3Reliability
If separate Vdd lowering circuit and negative bit line boost circuit are used, then write assist function is achieved, but IC area increases
Solution Approach 1:
The patent merges the Vdd lowering circuit and negative bit line boost circuit into a single integrated architecture. The same capacitor is used for both voltage reduction and bit line boosting, and the transistor networks are combined to provide dual functionality, significantly reducing the IC area required compared to separate circuit implementations.
Solution Approach 2:
The patent implements multi-functionality where a single circuit configuration performs both Vdd lowering and negative bit line boosting functions. The capacitor and transistor network serve dual purposes: reducing supply voltage during writes and providing negative voltage to bit lines, eliminating the need for separate dedicated circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces IC area and power usage, lowers system power consumption, and decreases package and cooling costs by enabling lower voltage operation without performance degradation.
Implementation Method 1
A write assist circuit includes a capacitor and a transistor circuit. The transistor circuit is configured to couple the capacitor to a memory cell supply voltage node to lower a supply voltage at the memory cell supply voltage node
Implementation Method 2
The transistor circuit is configured to couple the capacitor to a write driver to drive a bit line to a voltage level below ground
Data Source
AI summary
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.