SRAM Write-Assist Capacitor Selection for Efficient NBL Boost
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Solution Overview
Problem
Existing SRAM compilers inefficiently use multiple coupling capacitors for write-assist, leading to unnecessary power and area consumption due to unused capacitors acting as loads during NBL drive operations.
Innovation Solution
Deselect unused coupling capacitors by driving their drive terminals to a high impedance state, isolating them from the NBL drive process, and using selected capacitors to achieve efficient NBL write-assist with smaller capacitors at lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple coupling capacitors are used to target different bit-line lengths in compiler space, then write-assist coverage is improved, but power consumption increases due to unused capacitors acting as loads
Solution Approach 1:
The patent extracts the harmful load effect of unused coupling capacitors by isolating them from the NBL drive circuit. Specifically, the drive terminal of unused capacitors is disconnected from the active NBL drive network, removing their parasitic capacitance from the critical signal path while preserving their availability for future use when needed.
Solution Approach 2:
The patent implements dynamic selection of coupling capacitors based on actual write-assist needs. The system transitions capacitor terminals between connected and disconnected states, allowing the circuit to adapt its configuration dynamically - connecting only the necessary capacitors for the current operation and disconnecting others to eliminate their load effect.
2Manufacturing precision
If multiple coupling capacitors are used to accommodate varying bit-line loads, then NBL drive optimization is improved, but area consumption increases
Solution Approach 1:
The patent employs dynamic switching mechanisms that allow a fixed set of coupling capacitors to serve multiple operational modes. By dynamically connecting or disconnecting capacitor terminals, the system optimizes NBL drive for different bit-line lengths without requiring dedicated capacitors for each possible configuration, thereby reducing total area.
Solution Approach 2:
Each coupling capacitor in the system is designed to serve multiple functions across different operating conditions. The same physical capacitor can be activated for short bit-lines, medium bit-lines, or long bit-lines depending on the trim configuration and operational requirements, maximizing the utility of each capacitor instance and reducing the total number needed.
3Force
If larger coupling capacitors are used to compensate for high parasitic capacitance, then NBL bump magnitude is improved, but power consumption and area increase
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial selection criterion. Rather than attempting to overcome parasitic capacitance with larger capacitors, the system identifies and activates only those capacitors whose parasitic effects are acceptable for the given operating conditions, thereby eliminating the need for oversized compensation capacitors.
Solution Approach 2:
The patent applies different capacitor selections based on local operating conditions such as bit-line length and load characteristics. Instead of using a uniformly large capacitor to handle the worst-case scenario, the system locally optimizes by selecting appropriate capacitor values and combinations for each specific operating point, minimizing power consumption while maintaining adequate NBL bump magnitude.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the efficiency of the write-assist scheme by reducing loading and power consumption while maintaining effective NBL bump generation.
Implementation Method 1
A momentary negative bit-line with a positive word line (WL) voltage results in higher overdrive voltage for the pass-gate and eventually makes a successful write operation as it pulls down the internal node to the trip point easily.
Data Source
AI summary
In one aspect, a method of controlling the unused coupling capacitors to boost the efficiency of write-assist scheme in SRAM compiler space, includes the steps of: deselecting the plurality of unused coupling capacitors in an SRAM compiler-generated instance; driving the drive terminal of unused and deselected coupling capacitors a high impedance and making it float; while the negative bit-line drive for write assist is performed through a plurality of selected coupling capacitors. The unused coupling capacitors with one terminal floating do not load on the negative bit-line drive process which results in the negative bit-line write assist scheme operating more efficiently to produce a higher negative bump with smaller coupling capacitors at lower power consumption as the system operates at reduced loading.