SRAM Write Assist Circuits for Bitline Resistance Reduction
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Solution Overview
Problem
Existing SRAM memory systems face challenges in write operations due to the relative strength of NMOS access transistors compared to PMOS pull-up transistors, leading to issues with write assist techniques not scaling well, especially in advanced device technologies like FinFET.
Innovation Solution
The implementation of a memory system with a first and second write assist circuit configured to assist writing to different groups of memory cells, utilizing boost capacitors and write and boost logic at both ends of bitlines to reduce resistive losses and enhance write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NMOS access transistors are made stronger to improve read operation, then read speed is improved, but write operation fails because pull-up PMOS transistors become insufficient
Solution Approach 1:
The memory array is divided into multiple banks, each with independent write assist circuits. This segmentation allows different write assist strategies to be applied to different regions simultaneously, resolving the conflict between read and write requirements in different parts of the memory array.
Solution Approach 2:
Write assist circuits are introduced as intermediary components between the write driver and memory cells. These circuits provide additional current boosting and control mechanisms that enable successful write operations without requiring the NMOS access transistors to be weaker, thus maintaining both read speed and write reliability.
2Reliability
If write assist techniques are implemented to improve write operation, then write reliability is improved, but device complexity increases and scaling becomes difficult
Solution Approach 1:
The write assist circuits are designed to serve multiple functions: they provide current boosting for weak write operations, enable scaling to advanced process nodes, and can be selectively activated based on process corner conditions. This multi-functionality reduces overall system complexity by consolidating multiple potential solutions into a single versatile circuit block.
Solution Approach 2:
The write assist circuits utilize controllable current boosting parameters that can be adjusted based on process variations and operating conditions. By changing electrical parameters rather than structural configurations, the circuits adapt to different conditions without increasing physical complexity, enabling easy scaling to advanced process nodes.
3Reliability
If single write assist circuit is used to assist writing to memory cells, then write operation is improved for one group of cells, but other groups of cells lack write assistance
Solution Approach 1:
The memory array is divided into multiple banks, each with independent write assist circuits. This segmentation allows different write assist strategies to be applied to different regions simultaneously, resolving the conflict between read and write requirements in different parts of the memory array.
Data Source
AI summary
A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.