SRAM Write Assist Charge Controller for Bit-Line Stability
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Solution Overview
Problem
Conventional SRAM devices face challenges in maintaining write performance and cell stability due to issues with bit-line floating and voltage breakdown during negative bit-line write assist operations, particularly in multi-port memory designs, where the bit line potential can rise above zero, leading to unsuccessful writes and potential transistor failures.
Innovation Solution
The implementation of a memory circuit with a charge supply controller that disables charge supply to the bit lines after a determined period, using dummy bit lines to simulate short-circuit conditions and control the charge supply, thereby preventing bit-line floating and voltage breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative charge is supplied to the bit line to improve write performance, then the bit-line potential decreases below ground, but the bit line can float and the negative charge is lost, causing the bit line potential to rise above zero and leading to unsuccessful write operations
Solution Approach 1:
The patent employs a charge supply controller that monitors the write operation status and dynamically adjusts the charge supply to the bit line. When a write operation is detected, the controller supplies negative charge to boost the write margin; when the write operation completes or is aborted, the controller stops the charge supply to prevent bit line floating and potential rise, thus maintaining bit-line potential stability while ensuring write operation success
Solution Approach 2:
The system transitions from a static charge supply approach to a dynamic one where the charge pump is selectively activated only during write operations. This dynamic control ensures that the bit line receives the necessary negative charge boost only when needed, preventing charge loss due to floating and avoiding potential rise that would cause write failures
2Reliability
If a relatively larger negative charge is supplied to keep the bit line potential low for a longer period, then the write operation reliability improves, but voltage breakdown of transistors occurs causing failures in the memory cell
Solution Approach 1:
The patent applies negative charge to the bit line only partially - specifically during the write operation window - rather than continuously or excessively. The charge supply controller activates the charge pump only when a write operation is detected and deactivates it when the write operation completes or is aborted, providing just enough negative charge to ensure write success without causing transistor voltage breakdown
Solution Approach 2:
The system detects the write operation in advance and prepares the charge supply accordingly. The charge pump is activated before the write operation begins and deactivated after it completes, ensuring that negative charge is present on the bit line only during the critical write window, preventing both write failures and voltage breakdown
3Stability of the object's composition
If regulated boost potential is used to provide constant negative potential, then the bit-line potential stability improves, but additional power supply and regulator circuitry are required increasing device complexity
Solution Approach 1:
The charge supply controller uses the existing write operation detection mechanism and memory cell structure to automatically control the charge pump activation and deactivation. The system self-regulates the negative charge supply based on the write operation status without requiring external regulated power supplies or additional regulator circuitry, maintaining bit-line potential stability while avoiding increased device complexity
Data Source
AI summary
A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.