SRAM Core-Power Lowering Write Assist With Current Mirror Control
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Solution Overview
Problem
Current core power lowering (CPL) write assist techniques in SRAM memory increase operating speed but come at the cost of appreciable power discharge to ground, leading to high power consumption.
Innovation Solution
A current mirror is used to control the current conducted by a head-switch transistor during the CPL write assist period, reducing the core memory power voltage while minimizing power consumption by limiting the current discharge to ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CPL transistor M1 is made larger to discharge more current for faster voltage lowering, then write speed is improved, but power consumption increases significantly
Solution Approach 1:
A current mirror circuit is introduced as an intermediary between the CPL transistor and ground. The current mirror (comprising transistors M3 and M4) mediates the current flow, allowing the CPL transistor to discharge current through a controlled path that limits the total current to a predetermined level, thus preventing excessive power consumption while maintaining write speed improvement
Solution Approach 2:
The invention changes the parameter of current discharge by using the current mirror to enforce a predetermined current limit. Instead of allowing uncontrolled current discharge that would consume excessive power, the system transforms the discharge characteristic to maintain a balanced current level that achieves both speed improvement and power efficiency
2Speed
If NMOS access transistor is made larger to overcome PMOS transistor during write cycle, then write speed is improved, but memory density decreases due to increased die area
Solution Approach 1:
The invention applies local quality by selectively lowering the core memory power supply voltage only during the write assist period for specific bitcells that need writing. This localized voltage reduction weakens only the PMOS transistors in the targeted bitcells, allowing smaller NMOS access transistors to achieve the same write capability without increasing overall die area
Solution Approach 2:
The system performs preliminary action by pre-lowering the core memory power supply voltage before the actual write operation begins. The CPL transistor activates early to reduce the voltage, weakening the PMOS transistors in advance, so that when the write cycle starts, the NMOS access transistor can more easily flip the bitcell without needing to be oversized
Data Source
AI summary
A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.