SRAM Write-Assist Data Line Coupling Circuit
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Solution Overview
Problem
In deep sub-micron technology, the lowered word line voltage affects the write capability of SRAM cells, making traditional write-assist schemes like the negative-bit-line (NBL) scheme, which uses a MOS capacitor, neither area-efficient nor power-efficient.
Innovation Solution
A data line control circuit using write-assist data line coupling, where a write-assist data line is isolated from differential data lines and driven to a voltage transition, inducing a voltage transition in adjacent data lines via capacitive coupling, thereby creating a negative bit line without using a MOS capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a MOS capacitor is used in the traditional NBL scheme to provide negative voltage to bit lines, then the write capability of SRAM cells is improved, but the area occupied and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the MOS capacitor component from the traditional NBL scheme. Instead of using a dedicated MOS capacitor to generate negative voltage, the invention uses the inherent parasitic capacitance between adjacent data lines to achieve the same voltage pumping effect, thereby removing the area-consuming component while maintaining write capability
Solution Approach 2:
The patent makes the data lines serve multiple functions: they not only transmit data signals but also act as charge-pumping capacitors through their parasitic capacitance. This multi-functionality eliminates the need for dedicated capacitor structures, reducing overall circuit area while maintaining the negative bit line generation capability
2Reliability
If a MOS capacitor is used in the traditional NBL scheme to provide negative voltage to bit lines, then the write capability of SRAM cells is improved, but the power consumption increases
Solution Approach 1:
The patent implements a self-service mechanism where the data lines themselves provide the charge-pumping function through their parasitic capacitance. The voltage transitions on data lines automatically generate the negative voltage on complementary bit lines without requiring additional power-consuming capacitor charging/discharging operations, thus reducing overall power consumption while maintaining write capability
3Reliability
If transistor sizing is increased to enhance write capability in deep sub-micron technology, then the write capability is improved, but the area occupied increases
Solution Approach 1:
The patent changes the voltage parameter by generating negative voltage on bit lines through capacitive coupling rather than relying on increased transistor sizing. This parameter change (voltage level modification) enhances write capability without increasing transistor dimensions or occupying additional area, addressing the limitations of deep sub-micron technology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the write capability of SRAM cells by providing a negative voltage to bit lines efficiently, reducing area and production costs compared to traditional methods.
Implementation Method 1
one of the first data line and the second data line has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling between said at least one write-assist data line and said one of the first data line and the second data line
Data Source
AI summary
A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.