SRAM Internal Voltage Line Floating for Stable Low-Voltage Writes
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Solution Overview
Problem
As semiconductor memory devices integrate more transistors, their characteristics become dispersed, degrading memory cell stability, and reducing power supply voltage for low power consumption can lead to data retention failures in memory cells.
Innovation Solution
A static memory device with a power supply control circuit that floats the internal voltage line during write operations, using PMOS and NMOS transistors to maintain a voltage level between the power supply voltage and a threshold voltage, thereby improving write stability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of semiconductor memory device is increased, then the transistor characteristics become widely dispersed, but memory cell stability degrades
Solution Approach 1:
The patent applies local quality by providing different power supply voltage levels to different parts of the memory device. Specifically, the bit cell receives a first power supply voltage level during normal operation, while receiving a second, higher power supply voltage level during write operations. This localized voltage adjustment compensates for the degraded transistor characteristics in highly integrated devices, improving write stability without affecting overall device integration.
2Use of energy by moving object
If power supply voltage is reduced for low power consumption, then power consumption decreases, but data retention failure occurs in memory cells
Solution Approach 1:
The patent implements periodic action by dynamically switching the power supply voltage level based on operational mode. During normal read operations, the memory cell operates at a lower first power supply voltage level to minimize power consumption. During write operations, the voltage is temporarily increased to a second power supply voltage level to ensure reliable data writing. This periodic voltage adjustment allows the device to achieve low power consumption while maintaining data retention reliability.
Data Source
AI summary
A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group.