SRAM Core Cell Write Assist via Row and Column Headers
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Solution Overview
Problem
Traditional SRAM cells require a minimum power supply voltage to function predictably, which limits the reduction of power consumption, as lower voltages can result in incorrect write operations due to current fighting between access transistors and pull-up transistors.
Innovation Solution
Incorporating a row header and column header in the SRAM cell design that control current flow from the power supply, allowing the access transistors to write values without overpowering the pull-up transistors, and utilizing a staggered timing sequence for write operations to ensure final voltage values are reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to lower power consumption, then power consumption decreases, but the SRAM cell cannot function predictably and write operations produce incorrect results
Solution Approach 1:
The row header and column header transistors are turned off before the access transistors are activated during write operations. This preliminary action removes the conflicting current paths before the write operation begins, allowing the access transistors to write without fighting the pull-up transistors, thereby enabling lower voltage operation while maintaining reliable write functionality
Solution Approach 2:
The harmful current paths through the row header and column header transistors are extracted and removed from the active circuit during write operations. By making these transistors inactive before access transistors turn on, the patent eliminates the current fighting problem that previously prevented low-voltage operation, thus enabling both low power consumption and reliable operation
2Reliability
If the power supply voltage is maintained at minimum value to ensure predictable operation, then SRAM cell functions reliably, but power consumption cannot be reduced
Solution Approach 1:
The row header and column header transistors are turned off in advance before the access transistors are activated. This preliminary action eliminates the current fighting problem that previously required minimum voltage operation, thereby enabling voltage reduction while maintaining reliable write operations
Solution Approach 2:
The conflicting current paths through the row header and column header transistors are removed from the active circuit during write operations. This extraction of harmful current paths eliminates the need for minimum voltage to prevent current fighting, allowing voltage reduction while preserving reliable operation
3Ease of operation
If access transistors are used to write values into storage nodes, then write operations can be performed, but current fighting between access transistors and pull-up transistors prevents operation at lower voltages
Solution Approach 1:
The row header and column header transistors are turned off before the access transistors are activated during write operations. This preliminary action removes the conflicting current paths before the write operation begins, allowing access transistors to write without fighting the pull-up transistors, thereby enabling lower voltage operation while maintaining write capability
Solution Approach 2:
The harmful current paths through the row header and column header transistors are extracted and removed from the active circuit during write operations. By making these transistors inactive before access transistors turn on, the patent eliminates the current fighting problem that previously prevented low-voltage operation, thus enabling both low power consumption and reliable operation
Data Source
AI summary
A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.