Negative Voltage Write Assist With Leakage Control for SRAM
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Solution Overview
Problem
The challenge of effectively and efficiently performing write operations in memory cells with reduced supply voltages, which can lead to increased power consumption and leakage currents, is addressed by incorporating a write assist circuit with a negative voltage generator and leakage control circuit to ensure proper data writing and reduce leakage currents.
Innovation Solution
A write assist circuit that includes a negative voltage generator to apply a negative voltage to bitlines during write operations and a leakage control circuit to minimize leakage currents by applying the negative voltage to the gate terminal of transistors, thereby ensuring effective and efficient write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If supply voltage is reduced to ensure transistor safety and reduce power consumption, then power consumption decreases, but write operation effectiveness deteriorates
Solution Approach 1:
The write assist circuit is segmented into multiple functional blocks: a negative voltage generator that creates a negative voltage signal, a selection circuit that selects between the negative voltage and ground based on write operation status, and a bitline coupling mechanism. This segmentation allows independent optimization of each block to achieve both low power consumption and effective write operations.
Solution Approach 2:
The negative voltage generator proactively generates a negative voltage signal before actual write operations to counteract the insufficient drive strength caused by reduced supply voltage. This preliminary anti-action compensates for the weakened write capability, ensuring that data can be effectively written to memory cells even at ultra-low voltage levels.
2Reliability
If negative voltage is generated to improve write operations, then write operation effectiveness improves, but leakage current increases
Solution Approach 1:
The circuit dynamically switches between different voltage states based on operational mode. During write operations, the selection circuit connects the negative voltage to the bitline to enhance write effectiveness. During non-write operations, it switches to ground connection to eliminate leakage paths. This dynamic switching mechanism adapts the voltage state to operational requirements, improving write performance while minimizing leakage.
Solution Approach 2:
The selection circuit receives feedback about the operational state (write vs. non-write) and adjusts the voltage connection accordingly. When a write operation is detected, the circuit activates the negative voltage connection; when not, it deactivates it. This feedback mechanism ensures that the negative voltage is applied only when necessary, preventing continuous leakage currents.
3Area of stationary object
If transistor dimensions are reduced to increase density, then component density increases, but supply voltage magnitude must decrease
Solution Approach 1:
The negative voltage generated by the write assist circuit acts as a counterweight to the reduced supply voltage magnitude. By superimposing the negative voltage on the bitline during write operations, the circuit creates an enhanced voltage differential that compensates for the weakened drive strength of scaled-down transistors, enabling effective write operations despite smaller voltage margins.
Data Source
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AI summary
A memory array includes a write assist circuit that helps ensure that write operations can be effectively and efficiently performed in spite of low voltage supply levels. The write assist circuit includes a negative voltage generator that generates a negative voltage during write operations and applies the negative voltage to a bitline coupled to a selected memory cell. The negative voltage helps ensure that data is quickly and properly written to the memory cell. The write assist circuit also includes a leakage control circuit that helps reduce leakages associated with generation of the negative voltage by applying the negative voltage to other portions of the memory array in order to reduce leakage currents.