SRAM Write Assist Circuit Voltage Boost Differential Splitting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SRAM technologies face challenges in achieving a balance between cell stability and read/write performance, as improvements in one factor often adversely impact the others, and there is a need for an efficient write assist mechanism to enable small device dimension SRAM cells with reduced static leakage power and enhanced reliability.
Innovation Solution
A method and circuit for SRAM arrays that includes a write driver with a common bit line supply and source node, utilizing voltage boost circuitry to temporarily boost voltages through isolation devices, with a clamping mechanism to prevent unintended device activation, and a delay stage inverter pair with boost capacitors to manage voltage differentials, ensuring enhanced reliability and write-ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If voltage boost circuitry is applied to SRAM cells to improve write-ability, then write performance is enhanced, but device reliability deteriorates due to excessive voltage differentials
Solution Approach 1:
The voltage boost differential is segmented and applied separately to the supply node and source node through independent boost circuitry. This divides the total voltage stress into two smaller increments, preventing excessive voltage differentials that would harm device reliability while still achieving the necessary write-ability enhancement.
Solution Approach 2:
The patent changes the voltage parameters dynamically by applying temporary boosts to the supply and source nodes during write operations. The boost amount is carefully controlled to provide sufficient write assistance without creating harmful voltage differentials, thus improving write performance while maintaining device reliability.
2Loss of energy
If SRAM cell size is reduced to save power and increase density, then static leakage power is reduced, but write-ability deteriorates
Solution Approach 1:
The voltage boost circuitry performs preliminary action by pre-charging the supply node and pre-discharging the source node before the actual write operation. This preliminary voltage preparation ensures that when the write operation occurs on the reduced-size SRAM cell, sufficient voltage differential is already present to overcome the weaker drive strength of smaller transistors, thereby maintaining write-ability despite reduced cell size.
Solution Approach 2:
The patent changes voltage parameters temporarily during write operations to compensate for the reduced transistor drive strength in smaller SRAM cells. By dynamically adjusting the supply and source voltages through boost circuitry, the effective voltage differential is increased to maintain write-ability in scaled-down cells without increasing their physical size.
3Stability of the object's composition
If pass gate devices are tuned for SRAM stability, then cell stability is improved, but write-ability deteriorates
Solution Approach 1:
The patent introduces dynamic voltage adjustment through boost circuitry that temporarily modifies the supply and source node voltages during write operations. This dynamic approach allows the pass gate devices to be optimized for stability under normal conditions while providing additional voltage assistance only when needed during writes, thus resolving the contradiction between stability and write-ability.
Solution Approach 2:
The voltage parameters at the supply and source nodes are changed dynamically during write operations through the boost circuitry. This parameter change provides temporary additional drive strength to overcome the limitations of pass gates tuned for stability, enabling both stable operation during reads and improved write-ability during write operations without requiring separate device sizing.
Data Source
AI summary
A method and circuit for implementing write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node. The circuit includes voltage boost circuitry that temporarily boosts the common bit line supply node above supply voltage and temporarily boosts the common bit line source node below source voltage through isolation devices for applying the boosted source and supply voltages to a selected SRAM cell during a write operation. Splitting the boost differential between the common bit lines decreases an overall device voltage differential for providing substantially enhanced reliability of the SRAM array.