SRAM Write Assist via Dynamic Voltage Boosting
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Solution Overview
Problem
SRAM circuits face challenges in maintaining stability and efficient writing operations as they scale smaller, leading to increased potential for data flip during read operations and write failures due to the conflict between speed and stability.
Innovation Solution
The method involves increasing both the low and high voltage supply to SRAM circuits during write operations, maintaining a constant voltage difference, and using a power management module to elevate these voltages, thereby providing a boost cell supply write assist that stabilizes the memory cells and aids in reliable writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SRAM circuit is scaled smaller to increase integration density, then the manufacturing capability and integration density are improved, but the stability of the memory cell deteriorates due to increased potential for data flip during read operations
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the supply voltage to the SRAM cell during write operations. A voltage boost is applied to increase the write margin and overcome the reduced stability caused by scaling, while normal operating voltage is maintained during read operations to preserve stability. This temporal parameter adjustment resolves the contradiction between achieving high integration density through scaling while maintaining sufficient write capability and cell stability.
2Speed
If the write operation speed is increased to improve productivity, then the write speed is improved, but the write reliability deteriorates due to insufficient time for stable latching
Solution Approach 1:
The patent implements dynamics by making the supply voltage time-dependent during write operations. The voltage is dynamically boosted during the critical write phase to ensure reliable latching, then returned to normal levels. This dynamic voltage adjustment allows for faster write operations while maintaining sufficient latching time and reliability, as the enhanced voltage margin compensates for the reduced operation time.
3Reliability
If the voltage margin between bit line voltage and cell voltage is increased to improve write capability, then the write assist capability is improved, but the power consumption increases due to larger voltage swings
Solution Approach 1:
The patent applies local quality by providing voltage boosting only to the specific SRAM cell being written, rather than increasing voltage across the entire memory array. The voltage margin is locally enhanced at the target cell during the write operation, improving write capability without causing excessive power consumption across the whole system. This localized approach allows write assist where needed while maintaining energy efficiency elsewhere.
Data Source
AI summary
A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit.