SRAM Write Assist Apparatus for Low Voltage Reliability
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Solution Overview
Problem
Lower operating voltages in SRAM memory chips reduce write and read margins, leading to less reliable operations due to decreased power consumption and reduced voltage levels.
Innovation Solution
A write assist apparatus is introduced, which employs a write assist voltage potential (Vwas) lower than the normal operating voltage (VDD) and a timing control unit to manage voltage levels during write operations, using a voltage divider and timer unit to adjust voltage levels and pulse widths, thereby improving write reliability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operating voltage is reduced to lower power consumption, then power consumption is improved, but write and read margins are reduced leading to lower reliability
Solution Approach 1:
The write assist apparatus performs preliminary action by pre-discharging the storage node before the actual write operation. The timer unit generates a pulse signal that activates the write assist circuitry in advance, allowing the bit line to discharge the storage node to a lower voltage level before the main write clock signal arrives. This preliminary discharge creates a larger voltage margin for the subsequent write operation, enabling reliable writes at lower operating voltages.
Solution Approach 2:
The write assist apparatus introduces dynamic voltage control by using a timer unit to generate pulse signals that vary in width based on the operating voltage. The pulse width is adjusted dynamically to ensure proper timing at different voltage levels. This dynamic adjustment allows the system to maintain optimal write margins across varying operating conditions while operating at reduced voltages.
2Use of energy by moving object
If operating voltage is reduced, then power consumption is lowered, but write operation speed is reduced due to lower voltage levels
Solution Approach 1:
The write assist apparatus performs preliminary discharge of the storage node before the main write operation. By pre-discharging the storage node to a lower voltage level using the timer unit and write assist circuitry, the voltage difference between the bit line and storage node is increased during the actual write operation. This larger voltage difference accelerates the charge transfer process, compensating for the lower operating voltage and maintaining write operation speed.
Solution Approach 2:
The write assist apparatus changes the voltage parameter dynamically during the write operation. The timer unit generates pulse signals that control the write assist circuitry to discharge the storage node to different voltage levels based on the operating voltage. This parameter change creates optimal conditions for fast charge transfer during the write operation, maintaining speed despite lower operating voltages.
3Use of energy by moving object
If lower operating voltages are used, then power consumption is reduced, but write reliability decreases due to reduced voltage margins
Solution Approach 1:
The write assist apparatus performs preliminary discharge of the storage node before the main write operation. The timer unit generates a pulse signal that activates the write assist circuitry in advance, allowing the bit line to discharge the storage node to a lower voltage level before the main write clock signal arrives. This preliminary discharge creates a larger voltage margin for the subsequent write operation, enabling reliable writes at lower operating voltages.
Solution Approach 2:
The write assist apparatus introduces an intermediary mechanism between the bit line and storage node. The timer unit and write assist circuitry act as intermediaries that control the discharge process. By using this intermediary mechanism, the system can prepare the storage node in advance and control the timing of the voltage change, ensuring reliable write operations even at reduced voltages where direct write operations would fail.
Data Source
AI summary
An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.