SRAM Write Assist Circuit Voltage Control
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Solution Overview
Problem
The miniaturization of semiconductor devices, such as SRAM memory modules, leads to reduced operation margins due to increased fluctuations in production, making it challenging to maintain consistent performance at low voltage levels, especially when different shaped memory arrays are integrated in a system-on-a-chip (SOC) environment.
Innovation Solution
The semiconductor device incorporates a configuration with multiple memory modules, each having write assist circuits that control the power supply voltage levels for SRAM memory cells and word drivers, allowing for adjustable voltage reduction periods and drive capabilities based on the number of word lines and bit lines, thereby enhancing the write and read margins and access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If voltage scaling is performed to reduce power consumption, then power consumption decreases, but operation margin is reduced due to increased fluctuations in production
Solution Approach 1:
The patent implements dynamic voltage control for memory cell power supply lines during write operations. The power supply voltage is temporarily reduced only when needed for write operations, while maintaining normal voltage for read operations and non-selected cells. This dynamic adjustment allows the system to operate at lower average voltages (reducing power consumption) while maintaining sufficient operation margin when required.
Solution Approach 2:
The patent changes the power supply voltage parameter of memory cells dynamically based on operation type (read/write) and selection status. By controlling the power supply voltage to be lowered only for selected memory cells during write operations, the system optimizes the balance between power consumption and operation margin, allowing voltage scaling benefits while maintaining reliability.
2Ease of manufacture
If a fixed write assist circuit design is used, then the circuit is simple to manufacture, but it cannot adapt to memory arrays with different numbers of word lines
Solution Approach 1:
The patent applies local quality by making the write assist circuit's power supply control specific to individual memory cell power supply lines. Each memory cell power supply line can be independently controlled based on its corresponding word line selection, allowing the same circuit design to adapt to different memory array configurations without requiring redesign, while maintaining manufacturing simplicity.
Solution Approach 2:
The write assist circuit is designed with universal functionality to work with memory arrays having different numbers of word lines. The control mechanism responds to word line selection signals and automatically adjusts the power supply voltage accordingly, making the circuit adaptable to various memory array configurations without requiring configuration-specific design changes.
3Quantity of substance
If the memory cell power supply line load is large, then more memory cells can be supported, but the voltage level takes longer to reach the desired level during write operations
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the write operation initiation and the memory cell power supply voltage adjustment. This control circuit detects word line selection signals and triggers the power supply voltage reduction, coordinating the voltage change with the write operation timing. This intermediary control ensures that even with large loads, the voltage reaches the desired level at the appropriate time for write operations.
Solution Approach 2:
The patent implements preliminary action by reducing the memory cell power supply voltage before or at the start of the write operation. The control circuit is designed to detect the word line selection signal and initiate voltage reduction in advance, ensuring that the voltage reaches the desired level timely even when the power supply line has large load from multiple memory cells.
Data Source
AI summary
There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.