SRAM Write Assist Voltage Regulation for Latch-Up Prevention
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Solution Overview
Problem
SRAM circuits face challenges in maintaining stable operation at lower voltages due to wide ranges of operating conditions, leading to issues like latch up and unintended bit line discharges, which are exacerbated by write assist circuits that struggle to control voltage output effectively.
Innovation Solution
A voltage regulated write assist circuit is introduced, utilizing a capacitor and transistor configuration to limit and control the pull-down voltage, with additional components like voltage regulators and delay circuits to manage the charge on the write assist capacitor, ensuring stable and controlled voltage levels for writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write assist circuit uses a capacitor to pull the voltage on the access terminals below the low voltage to ensure SRAM cell writeability, then the cell becomes writeable with good stability, but the voltage range becomes too wide causing latch up and unintended bit line discharges
Solution Approach 1:
The patent implements a feedback mechanism where the write assist circuit monitors the actual voltage level on the access terminal and dynamically adjusts the capacitor discharge amount accordingly. This feedback loop ensures the voltage is pulled down enough to enable writing but not so much that it causes latch up or disturbs other bit lines, thus resolving the contradiction between writeability and harmful effects.
Solution Approach 2:
The patent makes the write assist circuit dynamic by using voltage-sensing elements that adapt the capacitor discharge level in real-time based on operating conditions. Rather than using a fixed discharge amount, the circuit dynamically adjusts the pull-down voltage to match the specific cell state and operating conditions, preventing both insufficient writing and excessive voltage pull-down that causes harmful effects.
2Reliability
If the voltage is pulled down too close to the trip point of the cell to enable writing under all operating conditions, then writeability is improved, but the cell stability deteriorates and latch up occurs
Solution Approach 1:
The feedback mechanism senses the voltage level relative to the cell trip point and adjusts the capacitor discharge to maintain an optimal safety margin. This ensures the voltage is pulled down sufficiently for writing across all operating conditions while maintaining a buffer that prevents the voltage from getting too close to the instability region, thus preserving cell stability.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on operating conditions by using temperature-compensated and voltage-compensated circuits that adjust the capacitor charge/discharge characteristics. This allows the write assist circuit to adapt to varying operating conditions while maintaining the voltage within a safe range that ensures both writeability and stability.
3Use of energy by moving object
If lower operating voltages are used to reduce power requirements in integrated circuits, then power consumption is reduced, but the ability to operate SRAM circuits deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-charging the write assist capacitor to an optimized voltage level before the write operation begins. This pre-prepared energy reservoir ensures that when the write operation is initiated, there is sufficient voltage pull-down capability available even at lower operating voltages, thus maintaining SRAM circuit operability while benefiting from reduced power consumption.
Solution Approach 2:
The patent optimizes the voltage parameters of the write assist circuit by adjusting the capacitor charge voltage and discharge resistance based on the reduced operating voltage. This parameter optimization ensures that the write assist circuit provides adequate voltage pull-down at lower operating voltages to maintain reliable SRAM operation without requiring higher supply voltages that would increase power consumption.
Data Source
AI summary
Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write assist circuit further includes a transistor to receive an enable signal to couple the bit line to a low voltage rail. A voltage source is provided to charge the capacitor. The voltage produced by the voltage source is limited to limit the pull down voltage at the discharge node from the write assist capacitor.