SRAM Write Back Circuit for Low Voltage Read Stability
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Solution Overview
Problem
SRAM memory cells experience read failures and unreliable data retrieval at low operating voltages due to voltage threshold issues, leading to conductivity problems and state flipping during read operations.
Innovation Solution
Incorporating a write back feature that allows data read from a memory cell to be written back during the read cycle using feedback lines and a keeper circuit, which maintains bit line voltages and prevents state flipping, enabling operation at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory operating voltage is reduced to save power, then energy consumption decreases, but read reliability deteriorates due to voltage threshold issues causing state flipping
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to a specific voltage level before the read operation begins. This precharging ensures that when the read operation starts at low voltage, the bit lines are already in a stable state, preventing the voltage threshold issues that cause state flipping. The precharge phase prepares the circuit in advance to handle the low-voltage read operation reliably.
Solution Approach 2:
The patent implements feedback by monitoring the voltage levels on the bit lines during the read operation and dynamically adjusting the read timing and voltage levels accordingly. This feedback mechanism allows the system to detect when voltage thresholds are approaching critical levels and adjust the read operation to maintain reliability, enabling stable operation at lower voltages without state flipping.
2Use of energy by stationary object
If the operating voltage approaches threshold levels, then power consumption is reduced, but conductivity problems increase causing read failures
Solution Approach 1:
The patent applies dynamics by making the read operation adaptive to changing voltage conditions. The read timing and voltage levels are dynamically adjusted based on the actual operating voltage and the state of the bit lines. This dynamic adjustment allows the system to maintain reliable reads even when operating voltage approaches threshold levels, preventing read failures while keeping power consumption low.
Solution Approach 2:
The patent changes key parameters such as bit line precharge voltage, read timing, and sense amplifier activation thresholds to optimize operation at low voltages. By adjusting these parameters dynamically based on operating conditions, the system maintains read reliability even when the operating voltage is close to the transistor threshold voltages, preventing conductivity problems from causing read failures.
3Device complexity
If standard read operation is used at low voltage, then simplicity is maintained, but read disturb effects cause voltage state flipping
Solution Approach 1:
The patent applies preliminary action by performing a precharge phase before the actual read operation. During this precharge phase, the bit lines are charged to a predetermined voltage level, which stabilizes the voltage distribution in the circuit before the read operation begins. This preliminary action prevents read disturb effects from causing state flipping while adding minimal complexity to the overall read sequence.
Solution Approach 2:
The patent implements continuity of useful action by overlapping the precharge phase with the read operation in a continuous sequence. The bit lines remain actively managed throughout the entire read process, transitioning smoothly from precharge to read without interruption. This continuous action ensures data state stability by maintaining proper voltage levels throughout the operation, preventing read disturb effects while keeping the implementation simple.
Data Source
AI summary
A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.