SRAM Write Circuit for P-Type Access Transistor Cells
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Solution Overview
Problem
Conventional semiconductor memory devices using p-type transistors for access transistors in SRAM cells lack a detailed description of the peripheral circuit, particularly the write circuit.
Innovation Solution
A semiconductor memory device is designed with a specific configuration of p-type and n-type transistors forming memory cells and a write circuit, including a pulldown circuit, predischarge circuit, column selection circuit, and write driver, to facilitate efficient data writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a p-type transistor is used for the access transistor in an SRAM cell, then the write operation can be simplified, but the peripheral circuit configuration becomes complex and unreliable
Solution Approach 1:
The peripheral circuit is divided into distinct functional modules: a column selection circuit with p-type transistors for bit line selection, a predischarge circuit with n-type transistors for bit line discharge, and a pulldown circuit. This segmentation allows each module to perform its specific function reliably while working together to enable simplified write operations.
Solution Approach 2:
The patent introduces intermediate circuit elements including a column selection circuit that acts as a mediator between the write driver and the memory cell array, and a predischarge circuit that mediates the discharge of bit lines. These intermediary circuits enable the p-type access transistor configuration to work reliably by providing necessary control and preparation functions.
2Reliability
If the access transistor is configured with p-type, then conductance can be improved, but the peripheral circuit requires additional components increasing complexity
Solution Approach 1:
Different transistor types are used in different locations according to their optimal characteristics: p-type transistors are used in the column selection circuit where high conductance is needed for bit line selection, while n-type transistors are used in the predischarge circuit where fast switching and discharge are required. This local optimization of transistor types achieves high conductance without excessive overall complexity.
Solution Approach 2:
The patent optimizes the conductance parameter of the p-type access transistors by adjusting their physical dimensions and bias conditions, while also changing the operating parameters of the peripheral circuits (such as timing sequences and voltage levels) to work synergistically with the p-type configuration, thereby achieving high conductance with manageable complexity.
3Productivity
If conventional SRAM cell configuration is used, then the basic memory function is achieved, but write operation efficiency is insufficient
Solution Approach 1:
The predischarge circuit performs a preliminary action by discharging the bit line before the actual write operation. This preparation step ensures that the bit line is in the correct initial state, enabling the p-type access transistor to efficiently and reliably transfer data during the subsequent write operation, thereby improving both efficiency and reliability.
Solution Approach 2:
The column selection circuit provides feedback control by monitoring the state of the bit lines and adjusting the column selection signals accordingly. This feedback mechanism ensures that the correct columns are activated during write operations, improving write efficiency while maintaining data integrity and reliability through proper control.
Data Source
AI summary
A semiconductor memory device includes memory cells and a write circuit. Each of the memory cells includes p-type drive transistors, n-type load transistors, and p-type access transistors connected to a bit line pair. The write circuit includes a column selection circuit including p-type transistors and a predischarge circuit including n-type transistors.